<?xml version="1.0"?>
<rss version="2.0">
   <channel>
      <title>COMSM1302 26/27 - 7th week Q&amp;A by Alex Cockrean</title>
      <link>https://padlet.com/uob/s02416fg8494e6un5xya</link>
      <description>Ask questions here anonymously.   Most-liked questions will be answered in Q&amp;A session on Wednesday</description>
      <language>en-us</language>
      <pubDate>2026-09-29 11:03:32 UTC</pubDate>
      <lastBuildDate>2026-11-03 13:03:42 UTC</lastBuildDate>
      <webMaster>hello@padlet.com</webMaster>
      <image>
         <url></url>
      </image>
      <item>
         <title>x86 CISC/ RISC? </title>
         <author></author>
         <link>https://padlet.com/uob/s02416fg8494e6un5xya/wish/4129352844</link>
         <description><![CDATA[<p>x86-64 seems to be a CISC architecture(as per its wiki page) for its backward compatibility etc. Has Intel been doing some sort of hybrid design to make it more RISC-y over the past two decades?  </p>]]></description>
         <enclosure url="" />
         <pubDate>2026-11-03 13:03:41 UTC</pubDate>
         <guid>https://padlet.com/uob/s02416fg8494e6un5xya/wish/4129352844</guid>
      </item>
   </channel>
</rss>
