COMSM1302 26/27 - 3rd week Q&A by Alex Cockrean

Question

2026-10-06 11:56:18 UTC

When we implement the RAM load bit, we effectively steer or gate the clock signal to specific registers using demultiplexer logic. Doesn't gating a clock through combinational logic introduce dynamic hazards (clock glitches) due to unequal path delays, and what is the standard practice in hardware design to prevent accidental latching?

Do you have next2next comparisons on time diagrms between level-triggerring and edge-triggering?

2026-10-06 12:01:21 UTC

2026-10-06 12:28:06 UTC

Because a level-triggered latch stays 'transparent' for the entire high pulse of the clock, what prevents the output from racing through combinational logic and corrupting its own input before the clock goes low?

Create truth table and then kMap is generated and this helps on the types of gate needed such as NAND, NOT gates, etc. in circuit. How about multiplxer and demultiplxer? Can truth table help on deciding whether we need multiplxer/ demultiplxer or not?

2026-10-06 12:38:37 UTC