Paper 2 Revision - 2016 by Oli Howson https://padlet.com/oli1/67jo0lrrlolz AQA AS Computer Science en-us 2016-06-07 09:41:39 UTC 2023-02-14 02:38:09 UTC hello@padlet.com Data Representation oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113912312 2016-06-07 09:59:53 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113912312 Computer Systems oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113912426 2016-06-07 10:00:50 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113912426 Computer Organisation & Architecture oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113912499 2016-06-07 10:01:10 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113912499 Consequences oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113912527 2016-06-07 10:01:23 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113912527 Communication & Networking oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113912552 2016-06-07 10:01:34 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113912552 ajannidawodu https://padlet.com/oli1/67jo0lrrlolz/wish/113912594 2016-06-07 10:01:55 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113912594 oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113912749  ℕ = Natural numbers including 0 (0,1,2,3...) 
ℤ = Integers (-3,-2,-1,0,1,2,3...)
ℚ = Rational numbers - fractions (1/2, 1/4, 7/8...)
Irrational numbers - cannot be written as a fraction - √2
ℝ = Real numbers - all real world quantities
Ordinal numbers - positions in a set (1st, 2nd, 3rd...)]]> 2016-06-07 10:03:07 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113912749 Bases oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113915129 Always go decimal -> binary -> hexadecimal and vice versa, don't skip!
from binary, split into nibbles, 0-9 = 0-9, 10-15 = A-F, then join together.
Hex - saves space on SCREEN and REDUCES MISTAKES

]]> 2016-06-07 10:28:31 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113915129 Binary oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113915300 8 bits = MAX 255, TOTAL 256
Stick to ISO - 1000 = kilo, mega, etc, no 1024!
Unsigned binary = normal, positives only. 2's Complement = pos/neg - first bit is the sign bit (1 = negative)
Add and Multiply
Fixed point - start at 1 to left of point and 1/2 at right of point]]> 2016-06-07 10:31:18 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113915300 Error checking oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113915423 Parity - counts the number of 1s and makes MSB up to be odd or even depending on type. Odd number of errors only. no correction. 
Majority vote - sends each bit 3 times and uses majority, has correction. 
Check digits are a mathematical calculation.]]> 2016-06-07 10:33:11 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113915423 Image/Sound etc oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113915538 Digital = data, 1s/0s, Analogue = continuous signal.
ADC and DAC
Bitmap size = width + height + colour depth (+ metadata)
Colour depth - use binary TOTAL rule - 2 bits = 4 colours, 3 bits = 8 colours.
Sound - size = samples * resolution * seconds (bits) / 8 for bytes.
Nyquist = sample at double the maximum frequency so as not to lose quality]]> 2016-06-07 10:34:54 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113915538 Von Neumann vs. Harvard lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/113915658 Von Neumann:
Computer has a single storage memory system to store data and execute programs.
Processor needs two clock cycles to create an instruction. Pipelining the instructions isn't possible using this architecture. This means it can only execute one instruction at a time.
Within the first clock cycle, the processor will get the instruction from the memory and decode it. the next one the data required is taken from the memory. For every instruction this is repeated, and this is why it needs 2 cycles to complete an instruction.
Harvard:
Computer has two seperate memories, one for storing data, and one for storing programs.
Processor can complete an instruction within one cycle using pipelining strategies.
Within the first stage of the pipeline, the instruction needs to be executed can be taken from program memory. Within the second stage of the pipeline, data is taken from the data memory using the decoded instruction or address.
Most of the modern computing architectures are based on Harvard's Architecure, but the pipeling stages varies between them.]]> 2016-06-07 10:36:33 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113915658 Compression oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113915745 RLE - Run length encoding - eg 111100110111 would be 3x1, 2x0, 2x1, 1x0, 3x1]]> 2016-06-07 10:37:47 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113915745 Caesar Cipher oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113915815 Adds a set shift (A shift 3 = D), opposite to uncipher. Easily cracked using brute force or patterns. Can have variable shift for more complexity. ]]> 2016-06-07 10:38:48 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113915815 Hardware + Software oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113916041 HW - Physical equip
SW - Instructions that tell the HW what to do.]]> 2016-06-07 10:41:27 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113916041 Adding in Binary examples lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/113916245 00101101
00011001
__________
01000110

1011
1000
_____
10011

01110010
00011111
__________
10010001]]> 2016-06-07 10:43:55 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113916245 Classification of Software oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113916446 System = controls the way the system works
Application - for 'doing' things]]> 2016-06-07 10:46:20 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113916446 Boolean Logic oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113916936 DML - Do on a SECTION at a time if needed - Choose sections mathematically.
Invert whole lot, invert each half, change symbol. Do DML from outside inwards
Make sure you can expand - and make - brackets
Remember the identities]]> 2016-06-07 10:51:58 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113916936 Clock Speed lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/113917697 clock speed is the frequency of the computer, which is shown in hertz (Hz). Usually shown using megahertz (MHz) or gigahertz (GHz) and this determins the speed that everything gets executed in. This is due to it being the amount of cycles within a second.]]> 2016-06-07 11:00:26 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113917697 System Software  oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113917778 OS - provides a virtual machine (abstracts away from the HW)
Utility - manages the system (eg AV, defrag)
Library - eg windows libraries - can be used by multiple SW
Translators (compiler, interpreter, assembler)]]> 2016-06-07 11:01:10 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113917778 OS oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113917967 Creates a virtual machine
Hides the complexities
Resource managements (memory, CPU, I/O...)]]> 2016-06-07 11:03:03 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113917967 Classification of Languages oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113918040 LL - machine code + assembly (1:1)
HL - imperative (many:1)]]> 2016-06-07 11:03:57 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113918040 Translators oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113918139 Assembler - from assembly code mnemonics to object code 
Compiler - source code to object code 
Interpreter - line by line interpretation and execution
Byte code (intermediate) - closer to assembly/object but not specific to a processor family - uses a VM]]> 2016-06-07 11:04:47 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113918139 Health & Saftey lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/113918225 Employer:
Enployees have to be trained to use the equipment correctly.
Employees have to take regular breaks or regular changes in activity.
Employees have to take regular eye appointments and get glasses if needed.
Enployee:
Ask employer about problems that occur.
Uses equipment in a way that they're trained to use them.
Manufacturer:
Screens don't flicker, and the height is adjustable.
Keyboards have a matt surface to reduce glare.]]> 2016-06-07 11:05:30 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113918225 Laws of Boolean algebra clarket10 https://padlet.com/oli1/67jo0lrrlolz/wish/113918234 Annulment Law :
A . 0 = 0    A variable AND’ed with 0 is always equal to 0.
A + 1 = 1    A variable OR’ed with 1 is always equal to 1.

Identity Law:
A + 0 = A   A variable OR’ed with 0 is always equal to the variable.
A . 1 = A    A variable AND’ed with 1 is always equal to the variable.

Idempotent Law:
A + A = A    A variable OR’ed with itself is always equal to the variable.
A . A = A    A variable AND’ed with itself is always equal to the variable.

Complement Law:
A . NOT A = 0    A variable AND’ed with its complement is always equal to 0.
A + NOT A = 1    A variable OR’ed with its complement is always equal to 1.

Commutative Law:
A . B = B . A    The order in which two variables are AND’ed makes no difference.
A + B = B + A    The order in which two variables are OR’ed makes no difference.

Double Negation Law:
NOT !A = A     A double complement of a variable is always equal to the variable.

Distributive Law:
A(B + C) = A.B + A.C         (OR Distributive Law)
A + B.C = (A + B).(A + C)  (AND Distributive Law)
]]> 2016-06-07 11:05:37 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113918234 Data Protection lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/113919494 Data has to be obtained lawfully and fairly
Data has to be accurate and up to date
Data has to be within the rights of the person you're getting the data about
Data cannot be kept for a longer amount than needed]]> 2016-06-07 11:19:27 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113919494 Truth Tables & Logic Gates oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113919624 Open and click the pictures]]> 2016-06-07 11:21:02 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113919624 DO NOT USE TRUTH TABLES! oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/113920013 Unless you're testing a thought out - don't hand it in!]]> 2016-06-07 11:25:03 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/113920013 Internet lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/114063535 A global network o computers and network computers which all have a unique IP addresses and use TCP/IP.]]> 2016-06-08 10:54:39 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114063535 Gateway lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/114063848 This connects a network that uses different link layer protocols.]]> 2016-06-08 10:58:11 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114063848 Components oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114064003 Processor - does the calculations
Main memory - Holds data and instructions
Address bus - carries the address of data to be retrieved or stored
Data bus - carries the data between RAM and CPU
Control bus - carries instructions from CU to RAM, CPU etc
I/O controllers - interface between CPU and I/O devices.]]> 2016-06-08 10:59:44 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114064003 World Wide Web lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/114064295 This is a collection of web pages that all have hyperlinks to other pages. The web pages that are structured and formatted by HTML and are styler by using CSS]]> 2016-06-08 11:03:16 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114064295 Internet Service Provider (ISP) lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/114064493 Allows a person to access the internet.]]> 2016-06-08 11:05:31 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114064493 Router lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/114064661 This connects networks that use the same link of layer protocols]]> 2016-06-08 11:07:48 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114064661 Stored Program Concept oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114065741 Machine code instructions stored in main memory and fetched and executed serially by processor]]> 2016-06-08 11:18:33 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114065741 Processor and Components oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114065827 ALU - performs logical and arithmetic operations
Control Unit - Instructs components how to respond to instructions
Clock - issues a tick to ensure all components act in synchronisation
General Purpose Registers - Very fast memory located close to the CPU for general use.
Dedicated Registers - Program counter - keeps track of the next instruction to access/execute.
Current Instruction Register - Holds the current instruction to be executed.
Memory Address Register - holds the address of memory to be accessed.
Memory Buffer Register - collates data/instruction from memory until all available to be put in to CIR.
Status Register - keeps track of the state of the register and individual bits are set/read - eg 'carry' flag]]> 2016-06-08 11:19:41 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114065827 Fetch-Decode-Execute Cycle oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114066948 See 6.2 from http://filestore.aqa.org.uk/resources/computing/AQA-75162-SMS.PDF]]> 2016-06-08 11:37:15 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114066948 Processor Instruction Set oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114067055 Instruction set - list of instructions that the processor understands - specific to processor family. 
OPCODE (the thing to do)
OPERAND(S) (One more more things it can do it on/with)]]> 2016-06-08 11:37:46 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114067055 Addressing Modes oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114068002 Immediate - operand is the datum
Direct - operand is the memory or register address of the datum]]> 2016-06-08 11:52:29 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114068002 ajannidawodu https://padlet.com/oli1/67jo0lrrlolz/wish/114068387 2016-06-08 11:58:18 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114068387 Assembly Code Instructions oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114068595 2016-06-08 12:01:12 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114068595 Interrupts oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114068875 Interrupt is a hardware call to tell the CPU that something urgent needs doing. Stores current instruction pointer (on stack) and status register then loads new instruction etc from interrupt. When done all is restored from stack and memory.]]> 2016-06-08 12:03:27 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114068875 First-generation programming language lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/114068990 machine code and assembly code, where the code is written in instructions using hexadecimal or binary. It is the language that the computer can recognize and execute programs instantly.]]> 2016-06-08 12:04:44 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114068990 Factors Affecting Performance oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114069563 Multiple cores - multiple calculations at once
Cache memory - less time to retrieve regularly used instructions/data
Clock speed - more instructions carried out in a given period of time
Word length - Allows access to more RAM and larger/higher precision numbers in fewer clock cycles
Address bus width - allows more memory locations to be accessed
Data bus width - allows more data to be transferred in one go]]> 2016-06-08 12:09:54 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114069563 Input & Output Devices oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114070159 Barcode reader, Digital Camera, Laser printer, RFID (see youtube videos)]]> 2016-06-08 12:15:57 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114070159 Secondary Storage Devices oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114070216 Needed for low cost/large capacity storage, non-volatile. 
Know differences/pros/cons/ how they work - hard disk, optical disk (CD/DVD), SSD (not hybrid!) - see youtube videos.

CD - 700Mb - cheap - slow - can be damaged
DVD - 4-8-16Gb - cheap - slow - can be damaged
USB - up to 512Gb - relatively cheap - robust - medium speed
HDD - up to 4Tb - medium cost - fast - not robust]]> 2016-06-08 12:16:42 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114070216 Fetch-Decode-Execute Cycle lunsij10 https://padlet.com/oli1/67jo0lrrlolz/wish/114070591 FETCH:
o contents of PC transferred to MAR
o address bus used to transfer this address to main memory
o contents of addressed memory location moved into the MBR
o transfer of content used the data bus
o increment PC
o transfer content of MBR to CIR.
DECODE:
o decode instruction held by the CIR
o the control unit decodes the instruction
o instruction split into opcode and operand.
EXECUTE:
o if necessary, data is fetched
o the opcode identifies the instruction to execute / operation to perform
o execute instruction by relevant part of processor
o result stored in accumulator]]> 2016-06-08 12:19:21 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114070591 Think: oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114192654 What could be the impact of this on other people - in law - on people of certain ages, groups, ethnicity, society as a hole? Is this a good thing? Not ALL impacts are negative! If it is negative, what could be done to counteract it?]]> 2016-06-09 10:12:32 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114192654 Serial and Parallel oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114193232 Serial - one bit at a time.
Parallel - many bits at a time
Serial requires less hardware, less media, cheaper, simpler. Less likely to suffer from skew, cross-talk or de-synchronisation.
Synchronous - waits for acknowledgement, needs start and stop bits. Synchronised by external clock. 
Asynchronous - Sends data and then is able to do other things whilst waiting for replies etc.
See https://en.wikipedia.org/wiki/Comparison_of_synchronous_and_asynchronous_signalling for advantages/ disadvantages.
Start bit - dictates the start of a new byte of data
Stop bit - dictates that the byte of data being transmitted is finished.]]> 2016-06-09 10:17:41 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114193232 Communication Methods oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114194612 Baud rate - rate at which information is transferred - multiple bits per signal. 
Bit rate - rate of bits transferred per signal - multiplication of baud rate 
Bandwidth - the range of frequencies (each of which can carry one or more bits) on a channel down which data can be sent.
Latency - The time delay between an action being instantiated (caused) and its effect being seen - NOT the same as lag.
Protocol - an agreed set of rules followed by two or more devices when communicating.]]> 2016-06-09 10:37:49 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114194612 Network Topology oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114195544 Physical star - each device connected via a central hub. Data is sent to the hub and broadcast (hub) or directed (switch) to the other node(s). Simple to manipulate, requires planning, expensive to implement.
Logical bus - not a physical layout but the idea that data is passed from node to node until it reaches the required node.]]> 2016-06-09 10:54:33 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114195544 Types of Networking oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114195731 Peer-to-peer - every node is equal status - easy to setup but limited centralisation,  impacts on management, security, backup etc.
Client-Server - Central dedicated servers provide a service when requested by clients. Allows centralisation of management, security, backups, etc.]]> 2016-06-09 10:57:10 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114195731 Wireless Networking oli1 https://padlet.com/oli1/67jo0lrrlolz/wish/114196979 WiFi - local area network following international standards, connect and communicated without a physical connection.
Wireless Network Adaptor - Allows computer to access the network
Wireless Access Point - Allows the physical network to access the 'wireless' network (ie does the broadcasting)
WPA/WPA2 - WiFi protected access (encryption)
SSID Broadcast - shows the name of the network for people to try and connect to - if you don't know it you can't (easily) try and connect to it!
MAC White List - list of hardware IDs that are allowed to connect to the network.
CSMA/CA - Carrier Sense Multiple Access with Collision Avoidance]]> 2016-06-09 11:14:54 UTC https://padlet.com/oli1/67jo0lrrlolz/wish/114196979