# data[].attributes.body
-two part ( lead lag circuit and voltage divider)
-lead lag circuit connects +ve input and voltage divider connects -ve input.
-0 degree phase shift
-Acl is 3.
-self start acl >3
-sustain acl=3
-voltage divider , R1/R2=2

# data[].attributes.body
-2 parts of circuit: lead lag circuit and voltage divider
-The Close Loop Gain msut be, Acl = 3
-for voltage divider ,R1/R2=2
-Self- start : gain > 3
-Sustain oscillation : gain=3

# data[].attributes.body
-wien bridge consists of 2 parts of circuit;
Lead Lag Circuit
Voltage Divider
-Acl= 3
-For self start: gain>3
-For voltage divider: R1/R2=2

# data[].attributes.body
- One of the RD Feedback Circuit
- 2 parts, voltage divider and lead lag circuit
- To sustain the oscillation, gain  = 3
- For self-start, gain > 3

# data[].attributes.body
wein bridge oscillator
- one of RC feedback oscillator
-requires voltage divider and lead lag circuit
-requires positive feedback
-voltage divider controls the gain
-use zener diode during start up process
-acl = 3
-for voltage divider, R1/R2=2

# data[].attributes.body
To achieve Acl=3 , R3=2R4.
R3 and R4 limits the voltage gain.

# data[].attributes.body
fr = 1/2PiRC Where:

ƒr  is the Resonant Frequency in Hertz

R  is the Resistance in Ohms

C  is the Capacitance in Farads

# data[].attributes.body
1. Self- start : greater > 3
2. Sustain oscillation : Equal to 3

# data[].attributes.body
one of the type from oscillator with RC Feedback Circuit
closed loop gain of 3
gain >3 - growing oscillation
gain <3- decreasing oscillation
fundamental part - lead lag circuit
ratio of R3/R4 must be greater than 2

# data[].attributes.body
Have 2 types of circuit
- Voltage Divider
- lead lag circuit
The Close Loop Gain msut be 3, Acl = 3
When Acl greater than 3, this is to startup the oscillation and when Acl equal to 3, this is sustains the oscillation. when Acl lower than 3, the oscillation cannot operate anymore.

# data[].attributes.body
frequency wein bridge = 1/2 pai RC

# data[].attributes.body
~Sharveni~
1) The wien bridge circuit can defined as two part which as lead lag circuit and VDR.
2) Lead lag circuit connects from +ve input and vdr connects from -ve input.
3) 0 degree phase shift condition is met when the freq
4) unity gain condition in the feedback loop is met when Acl is 3.
5) when dc power supply applied first,  the zener diode open and the R3 will be in series with R1. So that the Acl will increase to more than 3 and beat up the oscillation.
6) when the o/p signal reaches the zener breakdown voltage , the zener will conduct and R3 will short then Acl will lowest to 3 and BA is 1 and osillation is sustained.

# data[].attributes.headline
What u can summarize from wien-bridge oscillator lecture?

# data[].attributes.subject
What u can summarize from wien-bridge oscillator lecture?