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Ιστοσελίδες- εφαρμογές  

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Ιστοσελίδες- εφαρμογές  

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Τι χρησιμοποιήσαμε για την διευκόλυνση  της συνεργασίας μας :

1.  Padlet ( ανακεφαλαίωση δεδομένων)

2. Messenger( τηλεδιασκέψεις)

3.  Facebook ( αναρτήσεις)

4.  Google Drive ( διαμοιρασμό  και αποθήκευση εικόνας)

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Περιγράψτε αν ήρθατε σε επικοινωνία με τοπικούς φορείς (δήμο, εταιρείες, ερευνητικά κέντρα, πανεπιστήμια, οργανισμούς) τόσο για τον εντοπισμό του προβλήματος και την ανάπτυξη της προτεινόμενης λύσης, όσο και για πιθανές μελλοντικές συνέργειες.

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Περιγράψτε αν ήρθατε σε επικοινωνία με τοπικούς φορείς (δήμο, εταιρείες, ερευνητικά κέντρα, πανεπιστήμια, οργανισμούς) τόσο για τον εντοπισμό του προβλήματος και την ανάπτυξη της προτεινόμενης λύσης, όσο και για πιθανές μελλοντικές συνέργειες.

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σχολεια

ΔΔΕ Δράμας

ΕΚΦΕ Δράμας, Καβάλας, Σερρών Ξάνθης ή και όλης της Ελλάδας

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Ποιος είναι ο αντίκτυπος στην κοινότητα από την προτεινόμενη λύση ή κατασκευή; 

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Ποιος είναι ο αντίκτυπος στην κοινότητα από την προτεινόμενη λύση ή κατασκευή; 

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Παρουσίαση στο σχολείο μας

στο 6ο Γυμνάσιο

στην Διευθύντρια ΔΔΕ Δράμας

Στο ΕΚΦΕ Δράμας

Στα μέσα κοινωνικής δικτύωσης

αναρτήσαμε βίντεο στο youtube

συγγραφη διδακτικού σεναρίου STEM

δημοσίευση στον τοπικό τύπο

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Ποια/ες τεχνολογίες χρησιμοποιήσατε για τη δημιουργία της κατασκευής σας;

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Ποια/ες τεχνολογίες χρησιμοποιήσατε για τη δημιουργία της κατασκευής σας;

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ηλεκτρικά κυκλώματα με διακόπτες και LED

simulator logical gates

TinkerCad

Fritzing

Padlet

Google drive

messager, email

λογικά κυκλώματα με τρανζιστορ

λογικα κυκλώματα ολοκληρωμένα

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Ποια είναι η ιδέα μέσω της οποίας θα εφαρμόσετε το STEM και τις εκθετικές τεχνολογίες για να αντιμετωπιστεί το εν λόγω πρόβλημα, ζήτημα ή πρόκληση;

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Ποια είναι η ιδέα μέσω της οποίας θα εφαρμόσετε το STEM και τις εκθετικές τεχνολογίες για να αντιμετωπιστεί το εν λόγω πρόβλημα, ζήτημα ή πρόκληση;

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Αναζητούμε τα θεμέλεια της λογικής των έξυπνων συσκευών. Η έρευνά μας μας οδήγησε στα λογικά κυκλώματα. Κατασκευάσαμε λογικά κυκλώματα με διακόπτες υλοποιώντας τις λογικές πύλες NOT, AND και OR. Στη συνέχεια κατασκευάσαμε λογικές πύλες με τα ολοκληρωμένα 7404, 7408 και 7432 αλλά και τις λογικές πύλες NAND με το 7400, XOR με το 7486 και NOR me to 7402. Αφού κατασκευάσαμε και κατανοήσαμε την λειτουργία των απλών λογικών πυλών με ολοκληρωμένα κυκλώματα προχωρήσαμε σε πιο σύνθετα έργα. Σχεδιάσαμε στο "TinkerCad" και υλοποιήσαμε σε breadboard ένα κύκλωμα ημιαθροιστή με τα ολοκληρωμένα 7408 και 7486. Η χαρά μας ήταν απερίγραπτη όταν κάναμε την πράξη 1+1=10! Προχωρήσαμε σε πιο σύνθετα κυκλώματα και σχεδιάσαμε έναν αθροιστή.

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Περιγράψτε την ομάδα μαθητών, τον τρόπο συνεργασίας και την ανάθεση ρόλων.

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Περιγράψτε την ομάδα μαθητών, τον τρόπο συνεργασίας και την ανάθεση ρόλων.

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3 μαθητές και ο υπεύθυνος εκπαιδευτικός

κατανομή ρόλων που οδηγουν σε μελλοντικά ενδιαφέροντα

Συνεργασία με padlet kai google drive

επικοινωνία με email, messager, viber

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Λέξεις κλειδιά

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Λέξεις κλειδιά

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Συνεργασία
επικοινωνία
δημιουργικότητα
έρευνα
κριτική σκέψη
επίλυση προβλημάτων
πληροφορική παιδεία
ρόλοι - επαγγέλματα

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Εκπαιδευτικά σενάρια ΣΤΕΜ

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Εκπαιδευτικά σενάρια ΣΤΕΜ

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Μη διδάσκετε τους μαθητές σας  γνώσεις, πυρπολείστε το μυαλό τους.

Τα εκπαιδευτικά σενάρια ΣΤΕΜ είναι μια καινοτόμος μέθοδος διδασκαλίας. Κύριο χαρακτηριστικό τους είναι ότι είναι διαθεματικά, εμπλέκουν δηλαδή τα επιστημονικά πεδία των φυσικών επιστημών της τεχνολογίας και της πληροφορικής, των μαθηματικών και των εφαρμοσμένων επιστημών της μηχανικής.

Το εκπαιδευτικό σενάριο υλοποιείται με την μέθοδο project, βασικό συστατικό της οποίας είναι η διατύπωση ενός ερωτήματος ή η διαπίστωση ενός προβλήματος που πρέπει να απαντηθεί η να επιλυθεί.

Ο εκπαιδευτικός δεν επιτελεί τον παραδοσιακό ρόλο να διδάσκει ένα αντικείμενο και να επιτηρεί την τάξη, αλλά ενθαρρύνει, καθοδηγεί και ανακαλύπτει μαζί με τους μαθητές του τη λύση στο ερώτημα ή πρόβλημα που έχει τεθεί.

Οι μαθητές εργάζονται σε ομάδες και αναλαμβάνουν ρόλους ανάλογα με τα ενδιαφέροντα και τις κλίσεις τους. Π.χ. μια ομάδα μαθητών που ενδιαφέρεται για τις θετικές επιστήμες μπορεί να μελετήσει το πρόβλημα από τη σκοπιά των θετικών επιστημών, να εφαρμόσει την επιστημονική μέθοδο, τη θεωρία, τις αρχές και τους νόμους της επιστήμης και να βρει μια λύση. Οι γκαντζετάκηδες  μπορούν να αναλάβουν τη λειτουργία των συσκευών που θα χρησιμοποιήσουμε (κάμερες, φωτογραφικές μηχανές, drone κ.τ.λ.), οι μαθητές με ευχέρεια λόγου θα αναλάβουν τα γραπτά κείμενα για να κοινοποιήσουμε τα αποτελέσματα της εργασίας μας ενώ όσων «πιάνουν τα χέρια τους» θα αναλάβουν τις κατασκευές και τα πειράματα. Τέλος οι μαθητές με καλλιτεχνικές δεξιότητες θα αναλάβουν να παρουσιάσουν την εργασία με έναν κομψό τρόπο. Οι μαθητές δηλαδή αναλαμβάνουν ρόλους σύμφωνα με τα ενδιαφέροντά τους , ρόλους που μπορεί να οδηγήσουν στη μελλοντική επιλογή επαγγέλματος.

Οι κύριες δεξιότητες που θα αναπτύξουν οι μαθητές είναι:

Έρευνα σε πηγές

Συνεργασία

Δημιουργικότητα

Επικοινωνία

Συνεργασία

Κριτική σκέψη

Επίλυση προβλημάτων

Χρήση τεχνολογίας (smartphone, tablet, arduino)

Πληροφορική παιδεία

Ρόλοι – επαγγέλματα

Κοινοποίηση αποτελεσμάτων στην κοινότητα

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A free, simple, online logic gate simulator. Investigate the behaviour of AND, OR, NOT, NAND, NOR and XOR gates. Select gates from the dropdown list and click "add node" to add more gates. Drag from the hollow circles to the solid circles to make connections. Right click connections to delete them. See below for more detailed instructions.

The demo above allows you to create sequences of logic gates to see how they behave when connected to various inputs and outputs. Initially, you are presented with a simple on/off input and an output. To connect them, click and drag from the hollow circle on the right side of the on/off switch, and release the mouse when you are over the solid circle on the left side of the "output" block.

For each of the logic gates, outputs are hollow circles, and inputs are solid circles. Our "on/off" switch and "output block" aren't actually logic gates, but they are required because they give us the 1s and 0s needed to see how the gates behave. Click the on/off switch and see what happens. It turns yellow. This is our way of differentiating between 0 (off) and 1 (on).

To add a new logic gate, or an additional input or output block, choose from the dropdown menu and then click "add node". The new node will be placed in the top left hand corner, and you can drag it to your desired position. To delete nodes, click the small cross in the top right corner of its enclosing box. To remove connections, you can click on the input (solid circle) and drag away and release, or alternatively you can right click anywhere on the connection.

If you need more space, click on the "Full screen mode" button which will increase the size of the workspace to fill the size of the window. Additionally, you can rename an output by double clicking on its label.

NOT Gate

The NOT gate is also known as an inverter because the output is the exact opposite of the input. It has one input and one output. The two possibilities are written out in the table below. Tables listing all logical possibilities like this are known as truth tables.

AND Gate

The AND gate has two inputs and one output. The output is 1 if both inputs are 1, and for all other cases the output is 0.

NAND Gate

The NAND gate behaves in the opposite fashion to an AND gate. You can think of it as an AND gate followed immediately by a NOT gate. Its output is 0 when the two inputs are 1, and for all other cases, its output is 1. The name NAND comes from joining NOT and AND. The symbol for NAND is the same as that for AND except for the addition of a small circle on the right side.

OR Gate

The OR gate has two inputs and one output. If at least one of the inputs is 1, then the output will be 1. If neither input is 1, the output will be 0.

NOR Gate

Just as the NAND gate could be thought of as an AND followed by a NOT, a NOR can be thought of as an OR also followed by a NOT.

XOR Gate

With an OR gate, if both inputs were 1, the output was 1. However, with an XOR, (exclusive OR), if both inputs are 1, the output is 0. For all other scenarios, the XOR behaves the same as the OR.

Credits

If you've found this educational demo helpful, please consider supporting us on Ko-fi.

Please enable JavaScript to view the comments powered by Disqus.

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A free, simple, online logic gate simulator. Investigate the behaviour of AND, OR, NOT, NAND, NOR and XOR gates. Select gates from the dropdown list and click

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TinkerCad προσομοιωτής ηλεκτρονικών κυκλωμάτων

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TinkerCad προσομοιωτής ηλεκτρονικών κυκλωμάτων

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Circuit design Semi Adder with ic7408 ic7486 | Tinkercad

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Circuit design Semi Adder with ic7408 ic7486 created by pazoulis with Tinkercad

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Ποιο είναι το πρόβλημα, ζήτημα ή πρόκληση που αντιμετωπίζετε στην τοπική σας κοινότητα ή την καθημερινή σας ζωή και θα σας απασχολήσει στο πλαίσιο του διαγωνισμού Generation Next;(200 λέξεις)

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Ποιο είναι το πρόβλημα, ζήτημα ή πρόκληση που αντιμετωπίζετε στην τοπική σας κοινότητα ή την καθημερινή σας ζωή και θα σας απασχολήσει στο πλαίσιο του διαγωνισμού Generation Next;(200 λέξεις)

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Πώς μπορούν οι έξυπνες συσκευές να είναι τόσο έξυπνες;

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Λογική πύλη OR 

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Λογική πύλη OR 

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Κύκλωμα με τους διακόπτες για είσοδο και έν LED για έξοδο

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Λογική Πύλη OR με διακόπτες και LED

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Λογική Πύλη OR με διακόπτες και LED

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στην εικόνα βλέπουμε πως μπορούμε να φτιάξουμε μια λογική πύλη OR με διακόπτες για την είσοδο και LED για την έξοδο

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Πώς είναι δυνατόν οι έξυπνες συσκευές να παίρνουν λογικές αποφάσεις;
Γιατί τα κινητά είναι τόσο έξυπνα;
Πώς γίνεται οι έξυπνες συσκευές να λαμβάνουν λογικές αποφάσεις;
Ποια είναι τα θεμέλια της λογικής των υπολογιστών;
Για να ξεκινήσει ένα πλυντήριο ρούχων πρέπει:
1. η πόρτα να είναι κλειστή
2. το νερό να έχει φτάσει μέχρι μια στάθμη
3. η μάζα των ρούχων να είναι μικρότερη από μια τιμή.
Πώς μπορεί το πλυντήριο να παίρνει μια λογική απόφαση;

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Λογική Πύλη AND με διακόπτες

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Λογική Πύλη AND με διακόπτες

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Κυκλωμα XOR που καναμε την Παρασκευη

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Κυκλωμα XOR που καναμε την Παρασκευη

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Κυκλωμα OR που καναμε την Παρασκευη

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Κυκλωμα OR που καναμε την Παρασκευη

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An adder is a digital circuit that performs addition of numbers. In many computers and other kinds of processors adders are used in the arithmetic logic units or ALU. They are also used in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators and similar operations.

Although adders can be constructed for many number representations, such as binary-coded decimal or excess-3, the most common adders operate on binary numbers. In cases where two's complement or ones' complement is being used to represent negative numbers, it is trivial to modify an adder into an adder-subtractor. Other signed number representations require more logic around the basic adder.

The half adder adds two single binary digits A and B. It has two outputs, sum ( S) and carry ( C). The carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum is . The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C. The Boolean logic for the sum (in this case S) will be whereas for the carry ( C) will be AB. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder. The half adder adds two input bits and generates a carry and sum, which are the two outputs of a half adder. The input variables of a half adder are called the augend and addend bits. The output variables are the sum and carry. The truth table for the half adder is:

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder adds three one-bit numbers, often written as A, B, and C in; A and B are the operands, and C in is a bit carried in from the previous less-significant stage. The full adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit output. Output carry and sum typically represented by the signals C out and S, where the sum equals .

A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with and .

In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple integrated circuit chips which contain only one gate type per chip.

A full adder can also be constructed from two half adders by connecting A and B to the input of one half adder, then taking its sum-output S as one of the inputs to the second half adder and C in as its other input, and finally the carry outputs from the two half-adders are connected to an OR gate. The sum-output from the second half adder is the final sum output ( S) of the full adder and the output from the OR gate is the final carry output ( C out). The critical path of a full adder runs through both XOR gates and ends at the sum bit s. Assumed that an XOR gate takes 1 delays to complete, the delay imposed by the critical path of a full adder is equal to

The critical path of a carry runs through one XOR gate in adder and through 2 gates (AND and OR) in carry-block and therefore, if AND or OR gates take 1 delay to complete, has a delay of

The truth table for the full adder is:

Ripple-carry adder

It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a C in, which is the C out of the previous adder. This kind of adder is called a ripple-carry adder (RCA), since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder (under the assumption that C in = 0).

The layout of a ripple-carry adder is simple, which allows fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 × 2 (for carry propagation in latter adders) = 65 gate delays. The general equation for the worst-case delay for a n-bit carry-ripple adder, accounting for both the sum and carry bits, is

A design with alternating carry polarities and optimized AND-OR-Invert gates can be about twice as fast.

Carry-lookahead adder

To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry-lookahead adders (CLA). They work by creating two signals ( P and G) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a 1), generated in that bit position (both inputs are 1), or killed in that bit position (both inputs are 0). In most cases, P is simply the sum output of a half adder and G is the carry output of the same adder. After P and G are generated, the carries for every bit position are created. Some advanced carry-lookahead architectures are the Manchester carry chain, Brent-Kung adder (BKA), and the Kogge-Stone adder (KSA).

Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry-skip (or carry-bypass) adder which will determine P and G values for each block rather than each bit, and the carry-select adder which pre-generates the sum and carry values for either possible carry input (0 or 1) to the block, using multiplexers to select the appropriate result when the carry bit is known.

By combining multiple carry-lookahead adders, even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of lookahead carry units.

Other adder designs include the carry-select adder, conditional sum adder, carry-skip adder, and carry-complete adder.

Carry-save adders

If an adding circuit is to compute the sum of three or more numbers, it can be advantageous to not propagate the carry result. Instead, three-input adders are used, generating two results: a sum and a carry. The sum and the carry may be fed into two inputs of the subsequent 3-number adder without having to wait for propagation of a carry signal. After all stages of addition, however, a conventional adder (such as the ripple-carry or the lookahead) must be used to combine the final sum and carry results.

A full adder can be viewed as a 3:2 lossy compressor: it sums three one-bit inputs and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of 101 results in an output of 1 + 0 + 1 = 10 (decimal number 2). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 lossy compressor, compressing four possible inputs into three possible outputs.

Such compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the carry-save adder. If the addends are four or more, more than one layer of compressors is necessary, and there are various possible designs for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.

Liu, Tso-Kai; Hohulin, Keith R.; Shiau, Lih-Er; Muroga, Saburo (January 1974). "Optimal One-Bit Full-Adders with Different Types of Gates". IEEE Transactions on Computers. Bell Laboratories: IEEE. C-23 (1): 63-70. doi:10.1109/T-C.1974.223778. ISSN 0018-9340. S2CID 7746693.

Lai, Hung Chi; Muroga, Saburo (September 1979). "Minimum Binary Parallel Adders with NOR (NAND) Gates". IEEE Transactions on Computers. IEEE. C-28 (9): 648-659. doi:10.1109/TC.1979.1675433. S2CID 23026844.

Mead, Carver; Conway, Lynn (1980) [December 1979]. Introduction to VLSI Systems (1 ed.). Reading, MA, USA: Addison-Wesley. Bibcode:1980aw...book.....M. ISBN 978-0-20104358-7.

Davio, Marc; Dechamps, Jean-Pierre; Thayse, André (1983). Digital Systems, with algorithm implementation (1 ed.). Philips Research Laboratory, Brussels, Belgium: John Wiley & Sons, a Wiley-Interscience Publication. ISBN 978-0-471-10413-1. LCCN 82-2710.

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An adder is a digital circuit that performs addition of numbers. In many computers and other kinds of processors adders are used in the arithmetic logic units or ALU. They are also used in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators and similar operations.

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Οθονη 7 ψηφιων

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Οθονη 7 ψηφιων

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A seven-segment display is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot matrix displays.

Seven-segment displays are widely used in digital clocks, electronic meters, basic calculators, and other electronic devices that display numerical information.

Seven-segment representation of figures can be found in patents as early as 1903 (in U.S. Patent 1,126,641), when Carl Kinsley invented a method of telegraphically transmitting letters and numbers and having them printed on tape in a segmented format. In 1908, F. W. Wood invented an 8-segment display, which displayed the number 4 using a diagonal bar ( U.S. Patent 974,943). In 1910, a seven-segment display illuminated by incandescent bulbs was used on a power-plant boiler room signal panel. They were also used to show the dialed telephone number to operators during the transition from manual to automatic telephone dialing. They did not achieve widespread use until the advent of LEDs in the 1970s.

Some early seven-segment displays used incandescent filaments in an evacuated bulb; they are also known as numitrons. A variation (minitrons) made use of an evacuated potted box. Minitrons are filament segment displays that are housed in DIP packages like modern LED segment displays. They may have up to 16 segments. There were also segment displays that used small incandescent light bulbs instead of LEDs or incandescent filaments. These worked similarly to modern LED segment displays.

Vacuum fluorescent display versions were also used in the 1970s.

Many early (c. 1970s) LED seven-segment displays had each digit built on a single die. This made the digits very small. Some included magnifying lenses onto the design in an attempt to make the digits more legible.

The seven-segment pattern is sometimes used in posters or tags, where the user either applies color to pre-printed segments, or applies color through a seven-segment digit template, to compose figures such as product prices or telephone numbers.

For many applications, dot-matrix LCDs have largely superseded LED displays in general, though even in LCDs, seven-segment displays are common. Unlike LEDs, the shapes of elements in an LCD panel are arbitrary since they are formed on the display by photolithography. In contrast, the shapes of LED segments tend to be simple rectangles, reflecting the fact that they have to be physically moulded to shape, which makes it difficult to form more complex shapes than the segments of 7-segment displays. However, the high recognition factor of seven-segment displays, and the comparatively high visual contrast obtained by such displays relative to dot-matrix digits, makes seven-segment multiple-digit LCD screens very common on basic calculators.

The seven-segment display has inspired type designers to produce typefaces reminiscent of that display (but more legible), such as New Alphabet, "DB LCD Temp", "ION B", etc.

Using a restricted range of letters that look like (upside-down) digits, seven-segment displays are commonly used by school children to form words and phrases using a technique known as " calculator spelling".

Seven-segment displays may use a liquid crystal display (LCD), a light-emitting diode (LED) for each segment, an electrochromic display, or other light-generating or controlling techniques such as cold cathode gas discharge (Panaplex), vacuum fluorescent (VFD), incandescent filaments (Numitron), and others. For gasoline price totems and other large signs, vane displays made up of electromagnetically flipped light-reflecting segments (or "vanes") are still commonly used. An alternative to the 7-segment display in the 1950s through the 1970s was the cold-cathode, neon-lamp-like nixie tube. Starting in 1970, RCA sold a display device known as the that used incandescent filaments arranged into a seven-segment display. In USSR, the first electronic calculator "Vega", which was produced from 1964, contains 20 decimal digits with seven-segment electroluminescent display.

In a simple LED package, typically all of the cathodes (negative terminals) or all of the anodes (positive terminals) of the segment LEDs are connected and brought out to a common pin; this is referred to as a "common cathode" or "common anode" device. Hence a 7 segment plus decimal point package will only require nine pins, though commercial products typically contain more pins, and/or spaces where pins would go, in order to match standard IC sockets. Integrated displays also exist, with single or multiple digits. Some of these integrated displays incorporate their own internal decoder, though most do not: each individual LED is brought out to a connecting pin as described.

Multiple-digit LED displays as used in pocket calculators and similar devices used multiplexed displays to reduce the number of I/O pins required to control the display. For example, all the anodes of the A segments of each digit position would be connected together and to a driver circuit pin, while the cathodes of all segments for each digit would be connected. To operate any particular segment of any digit, the controlling integrated circuit would turn on the cathode driver for the selected digit, and the anode drivers for the desired segments; then after a short blanking interval the next digit would be selected and new segments lit, in a sequential fashion. In this manner an eight digit display with seven segments and a decimal point would require only 8 cathode drivers and 8 anode drivers, instead of sixty-four drivers and IC pins. Often in pocket calculators the digit drive lines would be used to scan the keyboard as well, providing further savings; however, pressing multiple keys at once would produce odd results on the multiplexed display.

Although to a naked eye all digits of an LED display appear lit, only one digit is lit at any given time in a multiplexed display. The digit changes at a high enough rate that the human eye cannot see the flashing (on earlier devices it can be visible to peripheral vision).

The seven segments are arranged as a rectangle of two vertical segments on each side with one horizontal segment on the top, middle, and bottom. Often the rectangle is (slanted), which aids readability.[citation needed ] In most applications, the segments are of nearly uniform shape and size (usually elongated hexagons, though trapezoids and rectangles can also be used), though in the case of adding machines, the vertical segments are longer and more oddly shaped at the ends in an effort to further enhance readability. The seven elements of the display can be lit in different combinations to represent the Arabic numerals.

The segments are referred to by the letters A to G, where the optional decimal point (an "eighth segment", referred to as DP) is used for the display of non-integer numbers. A single byte can encode the full state of a 7-segment-display including the decimal point. The most popular bit encodings are gfedcba and abcdefg. In the gfedcba representation, a byte value of 0x06 would turn on segments 'c' and 'b', which would display a '1'.

The numerical digits 0 to 9 are the most common characters displayed on seven-segment displays. The most common patterns used for each of these is:

The numerals 6 and 9 may also be represented without a 'tail', and the numeral 7 represented with a 'tail':

In Unicode 13.0, 10 codepoints had been given for segmented digits 0-9 in the Symbols for Legacy Computing block, to replicate early computer fonts that included seven-segment versions of the digits. The recommendation shows the less-common design for 7. The characters are simulated here:

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

U+1FBFx

Four binary bits are needed to specify the numbers 0-9, but can also specify 10-15, so usually decoders with 4 bit inputs can also display Hexadecimal (Hex) digits. Today, a combination of uppercase and lowercase letters is commonly used for A-F; this is done to obtain a unique, unambiguous shape for each hexadecimal digit (otherwise, a capital 'D' would look identical to a '0' and a capital 'B' would look identical to an '8'). Also the digit '6' must be displayed with the top bar lit to avoid ambiguity with the letter 'b'.

The following lookup table may be useful for writing code to drive a 7-segment display.

Digit

Display

gfedcba

abcdefg

a

b

c

d

e

f

g

1

0x06

0x30

on

on

2

0x5B

0x6D

on

on

on

on

on

4

0x66

0x33

on

on

on

on

5

0x6D

0x5B

on

on

on

on

on

6

0x7D

0x5F

on

on

on

on

on

on

7

0x07

0x70

on

on

on

A

0x77

0x77

on

on

on

on

on

on

b

0x7C

0x1F

on

on

on

on

on

C

0x39

0x4E

on

on

on

on

d

0x5E

0x3D

on

on

on

on

on

E

0x79

0x4F

on

on

on

on

on

F

0x71

0x47

on

on

on

on

The above modern numerical scheme wasn't always followed in the past, and various other schemes could be found as well:

The Texas Instruments seven-segment display decoder chips 7446/7447/7448/7449 and 74246/74247/74248/74249 and the Siemens FLH551-7448/555-8448 chips used truncated versions of "2", "3", "4", "5" and "6" for digits A-E. Digit F (1111 binary) was blank.

The Toshiba seven-segment decoder chips TC5002 and TC5022 repeat the numbers 0 to 5 for digits A-F. They also display the number 7 with the additional segment "f".

Soviet programmable calculators like the Б3-34 used the symbols "−", "L", "C", "Г", "E", and " " (space), allowing the error message EГГ0Г to be displayed.

Many earlier chips provided logic designed for only for 0-9 and higher numbers produced whatever pattern resulted. The National Semiconductor MM74C912 displayed "o" for A and B, "−" for C, D and E, and blank for F. The CD4511 just displayed blanks. The MC14558 displays the number "1" on the left side of the display (using segments "e" and "f" instead of the usual "b" and "c").

Most letters of Latin alphabet can be reasonably implemented using seven segments. Though not every letter is available, it is possible to create many useful words. By choosing better synonyms, it is possible to work around many shortcomings of seven-segment alphabet encodings. Some letters ('O', 'I', 'S') look identical to numbers, though use of lower-case 'o' and 'i', or putting 'I' on the left as shown here, could be used instead:

Case

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

Upper

Lower

Short messages giving status information (e.g. "no dISC" on a CD player) are also commonly represented on 7-segment displays. In the case of such messages it is not necessary for every letter to be unambiguous, merely for the words as a whole to be readable.

Examples:

, , , , ,

, , , , , ,

, , , , ,

Seven-segment displays have also been used to show letters of the Cyrillic and Greek alphabets:

Case

А

Б

В

Г

Д

Е

Ё

Ж

З

И

Й

К

Л

М

Н

О

П

Р

С

Т

У

Ф

Х

Ц

Ч

Ш

Щ

Ъ

Ы

Ь

Э

Ю

Я

Upper

Lower

There are enough patterns to show all the letters but few representations are unambiguous and intuitive at the same time. When all letters need to be displayed on a device, sixteen-segment and dot matrix displays are better choices than seven-segment displays.

Seven segments are capable of displaying some punctuation glyph characters. The hex value for each Unicode character is shown, of which the lower 8-bits of most of these exist as ASCII characters too.

There are also fourteen and sixteen segment displays (for full alphanumerics); however, these have mostly been replaced by dot matrix displays. Twenty-two-segment displays capable of displaying the full ASCII character set were briefly available in the early 1980s, but did not prove popular.

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A seven-segment display is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot matrix displays. Seven-segment displays are widely used in digital clocks, electronic meters, basic calculators, and other electronic devices that display numerical information.

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A binary number is a number expressed in the or binary numeral system, a method of mathematical expression which uses only two symbols: typically "0" ( zero) and "1" ( one).

The base-2 numeral system is a positional notation with a radix of 2. Each digit is referred to as a bit, or binary digit. Because of its straightforward implementation in digital electronic circuitry using logic gates, the binary system is used by almost all modern computers and computer-based devices, as a preferred system of use, over various other human techniques of communication, because of the simplicity of the language and the noise immunity in physical implementation.

Negative numbers are commonly represented in binary using two's complement.

The modern binary number system was studied in Europe in the 16th and 17th centuries by Thomas Harriot, Juan Caramuel y Lobkowitz, and Gottfried Leibniz. However, systems related to binary numbers have appeared earlier in multiple cultures including ancient Egypt, China, and India. Leibniz was specifically inspired by the Chinese .

Arithmetic values thought to have been represented by parts of the Eye of Horus

The scribes of ancient Egypt used two different systems for their fractions, Egyptian fractions (not related to the binary number system) and Horus-Eye fractions (so called because many historians of mathematics believe that the symbols used for this system could be arranged to form the eye of Horus, although this has been disputed). Horus-Eye fractions are a binary numbering system for fractional quantities of grain, liquids, or other measures, in which a fraction of a hekat is expressed as a sum of the binary fractions 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64. Early forms of this system can be found in documents from the Fifth Dynasty of Egypt, approximately 2400 BC, and its fully developed hieroglyphic form dates to the Nineteenth Dynasty of Egypt, approximately 1200 BC.

The method used for ancient Egyptian multiplication is also closely related to binary numbers. In this method, multiplying one number by a second is performed by a sequence of steps in which a value (initially the first of the two numbers) is either doubled or has the first number added back into it; the order in which these steps are to be performed is given by the binary representation of the second number. This method can be seen in use, for instance, in the Rhind Mathematical Papyrus, which dates to around 1650 BC.

Daoist Bagua

The dates from the 9th century BC in China. The binary notation in the I Ching is used to interpret its quaternary divination technique.

It is based on taoistic duality of yin and yang. Eight trigrams (Bagua) and a set of 64 hexagrams ("sixty-four" gua), analogous to the three-bit and six-bit binary numerals, were in use at least as early as the Zhou Dynasty of ancient China.

The Song Dynasty scholar Shao Yong (1011-1077) rearranged the hexagrams in a format that resembles modern binary numbers, although he did not intend his arrangement to be used mathematically. Viewing the least significant bit on top of single hexagrams in Shao Yong's square and reading along rows either from bottom right to top left with solid lines as 0 and broken lines as 1 or from top left to bottom right with solid lines as 1 and broken lines as 0 hexagrams can be interpreted as sequence from 0 to 63.

The Indian scholar Pingala (c. 2nd century BC) developed a binary system for describing prosody. He described meters in the form of short and long syllables (the latter equal in length to two short syllables). They were known as laghu (light) and guru (heavy) syllables.

Pingala's Hindu classic titled Chandaḥśāstra (8.23) describes the formation of a matrix in order to give a unique value to each meter. "Chandaḥśāstra" literally translates to science of meters in Sanskrit. The binary representations in Pingala's system increases towards the right, and not to the left like in the binary numbers of the modern positional notation. In Pingala's system, the numbers start from number one, and not zero. Four short syllables "0000" is the first pattern and corresponds to the value one. The numerical value is obtained by adding one to the sum of place values.

The residents of the island of Mangareva in French Polynesia were using a hybrid binary- decimal system before 1450. Slit drums with binary tones are used to encode messages across Africa and Asia. Sets of binary combinations similar to the I Ching have also been used in traditional African divination systems such as Ifá as well as in medieval Western geomancy. The majority of Indigenous Australian languages use a base-2 system.

In the late 13th century Ramon Llull had the ambition to account for all wisdom in every branch of human knowledge of the time. For that purpose he developed a general method or 'Ars generalis' based on binary combinations of a number of simple basic principles or categories, for which he has been considered a predecessor of computing science and artificial intelligence.

In 1605 Francis Bacon discussed a system whereby letters of the alphabet could be reduced to sequences of binary digits, which could then be encoded as scarcely visible variations in the font in any random text. Importantly for the general theory of binary encoding, he added that this method could be used with any objects at all: "provided those objects be capable of a twofold difference only; as by Bells, by Trumpets, by Lights and Torches, by the report of Muskets, and any instruments of like nature". (See Bacon's cipher.)

John Napier in 1617 described a system he called location arithmetic for doing binary calculations using a non-positional representation by letters. Thomas Harriot investigated several positional numbering systems, including binary, but did not publish his results; they were found later among his papers. Possibly the first publication of the system in Europe was by Juan Caramuel y Lobkowitz, in 1700.

Gottfried Leibniz

Leibniz studied binary numbering in 1679; his work appears in his article Explication de l'Arithmétique Binaire (published in 1703). The full title of Leibniz's article is translated into English as the"Explanation of Binary Arithmetic, which uses only the characters 1 and 0, with some remarks on its usefulness, and on the light it throws on the ancient Chinese figures of Fu Xi". Leibniz's system uses 0 and 1, like the modern binary numeral system. An example of Leibniz's binary numeral system is as follows:

Leibniz interpreted the hexagrams of the I Ching as evidence of binary calculus. As a Sinophile, Leibniz was aware of the I Ching, noted with fascination how its hexagrams correspond to the binary numbers from 0 to 111111, and concluded that this mapping was evidence of major Chinese accomplishments in the sort of philosophical mathematics he admired. The relation was a central idea to his universal concept of a language or characteristica universalis, a popular idea that would be followed closely by his successors such as Gottlob Frege and George Boole in forming modern symbolic logic. Leibniz was first introduced to the through his contact with the French Jesuit Joachim Bouvet, who visited China in 1685 as a missionary. Leibniz saw the I Ching hexagrams as an affirmation of the universality of his own religious beliefs as a Christian. Binary numerals were central to Leibniz's theology. He believed that binary numbers were symbolic of the Christian idea of creatio ex nihilo or creation out of nothing.

[A concept that] is not easy to impart to the pagans, is the creation ex nihilo through God's almighty power. Now one can say that nothing in the world can better present and demonstrate this power than the origin of numbers, as it is presented here through the simple and unadorned presentation of One and Zero or Nothing.

George Boole

In 1854, British mathematician George Boole published a landmark paper detailing an algebraic system of logic that would become known as Boolean algebra. His logical calculus was to become instrumental in the design of digital electronic circuitry.

In 1937, Claude Shannon produced his master's thesis at MIT that implemented Boolean algebra and binary arithmetic using electronic relays and switches for the first time in history. Entitled A Symbolic Analysis of Relay and Switching Circuits, Shannon's thesis essentially founded practical digital circuit design.

In November 1937, George Stibitz, then working at Bell Labs, completed a relay-based computer he dubbed the "Model K" (for " Kitchen", where he had assembled it), which calculated using binary addition. Bell Labs authorized a full research program in late 1938 with Stibitz at the helm. Their Complex Number Computer, completed 8 January 1940, was able to calculate complex numbers. In a demonstration to the American Mathematical Society conference at Dartmouth College on 11 September 1940, Stibitz was able to send the Complex Number Calculator remote commands over telephone lines by a teletype. It was the first computing machine ever used remotely over a phone line. Some participants of the conference who witnessed the demonstration were John von Neumann, John Mauchly and Norbert Wiener, who wrote about it in his memoirs.

The Z1 computer, which was designed and built by Konrad Zuse between 1935 and 1938, used Boolean logic and binary floating-point numbers.

Any number can be represented by a sequence of bits (binary digits), which in turn may be represented by any mechanism capable of being in two mutually exclusive states. Any of the following rows of symbols can be interpreted as the binary numeric value of 667:

A binary clock might use LEDs to express binary values. In this clock, each column of LEDs shows a binary-coded decimal numeral of the traditional sexagesimal time.

The numeric value represented in each case is dependent upon the value assigned to each symbol. In the earlier days of computing, switches, punched holes and punched paper tapes were used to represent binary values. In a modern computer, the numeric values may be represented by two different voltages; on a magnetic disk, magnetic polarities may be used. A "positive", " yes", or "on" state is not necessarily equivalent to the numerical value of one; it depends on the architecture in use.

In keeping with customary representation of numerals using Arabic numerals, binary numbers are commonly written using the symbols 0 and 1. When written, binary numerals are often subscripted, prefixed or suffixed in order to indicate their base, or radix. The following notations are equivalent:

100101 binary (explicit statement of format)

100101b (a suffix indicating binary format; also known as Intel convention)

100101B (a suffix indicating binary format)

bin 100101 (a prefix indicating binary format)

100101₂ (a subscript indicating base-2 (binary) notation)

%100101 (a prefix indicating binary format; also known as Motorola convention)

0b100101 (a prefix indicating binary format, common in programming languages)

6b100101 (a prefix indicating number of bits in binary format, common in programming languages)

#b100101 (a prefix indicating binary format, common in Lisp programming languages)

When spoken, binary numerals are usually read digit-by-digit, in order to distinguish them from decimal numerals. For example, the binary numeral 100 is pronounced one zero zero, rather than one hundred, to make its binary nature explicit, and for purposes of correctness. Since the binary numeral 100 represents the value four, it would be confusing to refer to the numeral as one hundred (a word that represents a completely different value, or amount). Alternatively, the binary numeral 100 can be read out as "four" (the correct value), but this does not make its binary nature explicit.

Counting in binary is similar to counting in any other number system. Beginning with a single digit, counting proceeds through each symbol, in increasing order. Before examining binary counting, it is useful to briefly discuss the more familiar decimal counting system as a frame of reference.

Decimal counting uses the ten symbols 0 through 9. Counting begins with the incremental substitution of the least significant digit (rightmost digit) which is often called the first digit. When the available symbols for this position are exhausted, the least significant digit is reset to 0, and the next digit of higher significance (one position to the left) is incremented ( overflow), and incremental substitution of the low-order digit resumes. This method of reset and overflow is repeated for each digit of significance. Counting progresses as follows:

000, 001, 002, ... 007, 008, 009, (rightmost digit is reset to zero, and the digit to its left is incremented)

010, 011, 012, ...

...

090, 091, 092, ... 097, 098, 099, (rightmost two digits are reset to zeroes, and next digit is incremented)

100, 101, 102, ...

This counter shows how to count in binary from numbers zero through thirty-one.

A party trick to guess a number from which cards it is printed on uses the bits of the binary representation of the number. In the SVG file, click a card to toggle it

Binary counting follows the exact same procedure, and again the incremental substitution begins with the least significant binary digit, or bit (the rightmost one, also called the first bit), except that only the two symbols 0 and 1 are available. Thus, after a bit reaches 1 in binary, an increment resets it to 0 but also causes an increment of the next bit to the left:

0000,

0001, (rightmost bit starts over, and the next bit is incremented)

0010, 0011, (rightmost two bits start over, and the next bit is incremented)

0100, 0101, 0110, 0111, (rightmost three bits start over, and the next bit is incremented)

1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 ...

In the binary system, each bit represents an increasing power of 2, with the rightmost bit representing 2 ⁰, the next representing 2 ¹, then 2 ², and so on. The value of a binary number is the sum of the powers of 2 represented by each "1" bit. For example, the binary number 100101 is converted to decimal form as follows:

Fractions in binary arithmetic terminate only if 2 is the only prime factor in the denominator. As a result, 1/10 does not have a finite binary representation ( 10 has prime factors 2 and 5). This causes 10 × 0.1 not to precisely equal 1 in floating-point arithmetic. As an example, to interpret the binary expression for 1/3 = .010101..., this means: 1/3 = 0 × + 1 × + 0 × + 1 × + ... = 0.3125 + ... An exact value cannot be found with a sum of a finite number of inverse powers of two, the zeros and ones in the binary representation of 1/3 alternate forever.

Arithmetic in binary is much like arithmetic in other numeral systems. Addition, subtraction, multiplication, and division can be performed on binary numerals.

The circuit diagram for a binary half adder, which adds two bits together, producing sum and carry bits

The simplest arithmetic operation in binary is addition. Adding two single-digit binary numbers is relatively simple, using a form of carrying:

Adding two "1" digits produces a digit "0", while 1 will have to be added to the next column. This is similar to what happens in decimal when certain single-digit numbers are added together; if the result equals or exceeds the value of the radix (10), the digit to the left is incremented:

5 + 5 → 0, carry 1 (since 5 + 5 = 10 = 0 + (1 × 10¹) )

7 + 9 → 6, carry 1 (since 7 + 9 = 16 = 6 + (1 × 10¹) )

This is known as carrying. When the result of an addition exceeds the value of a digit, the procedure is to "carry" the excess amount divided by the radix (that is, 10/10) to the left, adding it to the next positional value. This is correct since the next position has a weight that is higher by a factor equal to the radix. Carrying works the same way in binary:

  1 1 1 1 1    (carried digits)
    0 1 1 0 1
+   1 0 1 1 1
-------------
= 1 0 0 1 0 0 = 36

In this example, two numerals are being added together: 01101 ₂ (13 ₁₀) and 10111 ₂ (23 ₁₀). The top row shows the carry bits used. Starting in the rightmost column, 1 + 1 = 10 ₂. The 1 is carried to the left, and the 0 is written at the bottom of the rightmost column. The second column from the right is added: 1 + 0 + 1 = 10 ₂ again; the 1 is carried, and 0 is written at the bottom. The third column: 1 + 1 + 1 = 11 ₂. This time, a 1 is carried, and a 1 is written in the bottom row. Proceeding like this gives the final answer 100100 ₂ (36 ₁₀).

When computers must add two numbers, the rule that: x xor y = (x + y) mod 2 for any two bits x and y allows for very fast calculation, as well.

Long carry method

A simplification for many binary addition problems is the "long carry method" or "Brookhouse Method of Binary Addition". This method is particularly useful when one of the numbers contains a long stretch of ones. It is based on the simple premise that under the binary system, when given a stretch of digits composed entirely of n ones (where n is any integer length), adding 1 will result in the number 1 followed by a string of n zeros. That concept follows, logically, just as in the decimal system, where adding 1 to a string of n 9s will result in the number 1 followed by a string of n 0s:

     Binary                        Decimal
    1 1 1 1 1     likewise        9 9 9 9 9
 +          1                  +          1
  -----------                   -----------
  1 0 0 0 0 0                   1 0 0 0 0 0

Such long strings are quite common in the binary system. From that one finds that large binary numbers can be added using two simple steps, without excessive carry operations. In the following example, two numerals are being added together: 1 1 1 0 1 1 1 1 1 0 ₂ (958 ₁₀) and 1 0 1 0 1 1 0 0 1 1 ₂ (691 ₁₀), using the traditional carry method on the left, and the long carry method on the right:

Traditional Carry Method                       Long Carry Method
                                vs.
  1 1 1   1 1 1 1 1      (carried digits)   1 ←     1 ←            carry the 1 until it is one digit past the "string" below
    1 1 1 0 1 1 1 1 1 01 1 1 0 1 1 1 1 1 0 cross out the "string", + 1 0 1 0 1 1 0 0 1 1 + 1 01 0 1 1 0 0 1 1 and cross out the digit that was added to it ----------------------- ---------------------- = 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 1

The top row shows the carry bits used. Instead of the standard carry from one column to the next, the lowest-ordered "1" with a "1" in the corresponding place value beneath it may be added and a "1" may be carried to one digit past the end of the series. The "used" numbers must be crossed off, since they are already added. Other long strings may likewise be cancelled using the same technique. Then, simply add together any remaining digits normally. Proceeding in this manner gives the final answer of 1 1 0 0 1 1 1 0 0 0 1 ₂ (1649 ₁₀). In our simple example using small numbers, the traditional carry method required eight carry operations, yet the long carry method required only two, representing a substantial reduction of effort.

Addition table

The binary addition table is similar to, but not the same as, the truth table of the logical disjunction operation . The difference is that , while .

Subtraction works in much the same way:

Subtracting a "1" digit from a "0" digit produces the digit "1", while 1 will have to be subtracted from the next column. This is known as borrowing. The principle is the same as for carrying. When the result of a subtraction is less than 0, the least possible value of a digit, the procedure is to "borrow" the deficit divided by the radix (that is, 10/10) from the left, subtracting it from the next positional value.

    *   * * *   (starred columns are borrowed from)
  1 1 0 1 1 1 0
−     1 0 1 1 1
----------------
= 1 0 1 0 1 1 1

  *             (starred columns are borrowed from)
  1 0 1 1 1 1 1
-   1 0 1 0 1 1
----------------
= 0 1 1 0 1 0 0

Subtracting a positive number is equivalent to adding a negative number of equal absolute value. Computers use signed number representations to handle negative numbers-most commonly the two's complement notation. Such representations eliminate the need for a separate "subtract" operation. Using two's complement notation subtraction can be summarized by the following formula:

Multiplication in binary is similar to its decimal counterpart. Two numbers A and B can be multiplied by partial products: for each digit in B, the product of that digit in A is calculated and written on a new line, shifted leftward so that its rightmost digit lines up with the digit in B that was used. The sum of all these partial products gives the final result.

Since there are only two digits in binary, there are only two possible outcomes of each partial multiplication:

If the digit in B is 0, the partial product is also 0

If the digit in B is 1, the partial product is equal to A

For example, the binary numbers 1011 and 1010 are multiplied as follows:

           1 0 1 1   (A) × 1 0 1 0 (B) --------- 0 0 0 0 ← Corresponds to the rightmost 'zero' inB + 1 0 1 1 ← Corresponds to the next 'one' inB + 0 0 0 0 + 1 0 1 1 --------------- = 1 1 0 1 1 1 0

Binary numbers can also be multiplied with bits after a binary point:

               1 0 1 . 1 0 1A (5.625 in decimal) × 1 1 0 . 0 1B (6.25 in decimal) ------------------- 1 . 0 1 1 0 1 ← Corresponds to a 'one' inB + 0 0 . 0 0 0 0 ← Corresponds to a 'zero' inB + 0 0 0 . 0 0 0 + 1 0 1 1 . 0 1 + 1 0 1 1 0 . 1 --------------------------- = 1 0 0 0 1 1 . 0 0 1 0 1 (35.15625 in decimal)

See also Booth's multiplication algorithm.

Multiplication table

The binary multiplication table is the same as the truth table of the logical conjunction operation .

Long division in binary is again similar to its decimal counterpart.

In the example below, the divisor is 101 ₂, or 5 in decimal, while the dividend is 11011 ₂, or 27 in decimal. The procedure is the same as that of decimal long division; here, the divisor 101 ₂ goes into the first three digits 110 ₂ of the dividend one time, so a "1" is written on the top line. This result is multiplied by the divisor, and subtracted from the first three digits of the dividend; the next digit (a "1") is included to obtain a new three-digit sequence:

              1
        ___________
1 0 1   ) 1 1 0 1 1
        − 1 0 1
          -----
          0 0 1

The procedure is then repeated with the new sequence, continuing until the digits in the dividend have been exhausted:

             1 0 1
       ___________
1 0 1  ) 1 1 0 1 1
       − 1 0 1
         -----
             1 1 1
         −   1 0 1
             -----
             0 1 0

Thus, the quotient of 11011 ₂ divided by 101 ₂ is 101 ₂, as shown on the top line, while the remainder, shown on the bottom line, is 10 ₂. In decimal, this corresponds to the fact that 27 divided by 5 is 5, with a remainder of 2.

Aside from long division, one can also devise the procedure so as to allow for over-subtracting from the partial remainder at each iteration, thereby leading to alternative methods which are less systematic, but more flexible as a result.

The process of taking a binary square root digit by digit is the same as for a decimal square root and is explained here. An example is:

             1 0 0 1
            ---------
           √ 1010001
             1
            ---------
      101     01
               0
             --------
      1001     100
                 0
             --------
      10001    10001
               10001
              -------
                   0

Though not directly related to the numerical interpretation of binary symbols, sequences of bits may be manipulated using Boolean logical operators. When a string of binary symbols is manipulated in this way, it is called a bitwise operation; the logical operators AND, OR, and XOR may be performed on corresponding bits in two binary numerals provided as input. The logical NOT operation may be performed on individual bits in a single binary numeral provided as input. Sometimes, such operations may be used as arithmetic short-cuts, and may have other computational benefits as well. For example, an arithmetic shift left of a binary number is the equivalent of multiplication by a (positive, integral) power of 2.

Conversion of (357)₁₀ to binary notation results in (101100101)

To convert from a base-10 integer to its base-2 (binary) equivalent, the number is divided by two. The remainder is the least-significant bit. The quotient is again divided by two; its remainder becomes the next least significant bit. This process repeats until a quotient of one is reached. The sequence of remainders (including the final quotient of one) forms the binary value, as each remainder must be either zero or one when dividing by two. For example, (357) ₁₀ is expressed as (101100101) 2.

Conversion from base-2 to base-10 simply inverts the preceding algorithm. The bits of the binary number are used one by one, starting with the most significant (leftmost) bit. Beginning with the value 0, the prior value is doubled, and the next bit is then added to produce the next value. This can be organized in a multi-column table. For example, to convert 10010101101 ₂ to decimal:

The result is 1197 ₁₀. The first Prior Value of 0 is simply an initial decimal value. This method is an application of the Horner scheme.

The fractional parts of a number are converted with similar methods. They are again based on the equivalence of shifting with doubling or halving.

In a fractional binary number such as 0.11010110101 ₂, the first digit is , the second , etc. So if there is a 1 in the first place after the decimal, then the number is at least , and vice versa. Double that number is at least 1. This suggests the algorithm: Repeatedly double the number to be converted, record if the result is at least 1, and then throw away the integer part.

For example, , in binary, is:

Converting

Result

0.

0.0

0.01

0.010

0.0101

Thus the repeating decimal fraction 0.3... is equivalent to the repeating binary fraction 0.01... .

Or for example, 0.1 ₁₀, in binary, is:

This is also a repeating binary fraction 0.00011... . It may come as a surprise that terminating decimal fractions can have repeating expansions in binary. It is for this reason that many are surprised to discover that 0.1 + ... + 0.1, (10 additions) differs from 1 in floating point arithmetic. In fact, the only binary fractions with terminating expansions are of the form of an integer divided by a power of 2, which 1/10 is not.

The final conversion is from binary to decimal fractions. The only difficulty arises with repeating fractions, but otherwise the method is to shift the fraction to an integer, convert it as above, and then divide by the appropriate power of two in the decimal base. For example:

Another way of converting from binary to decimal, often quicker for a person familiar with hexadecimal, is to do so indirectly-first converting ( in binary) into ( in hexadecimal) and then converting ( in hexadecimal) into ( in decimal).

For very large numbers, these simple methods are inefficient because they perform a large number of multiplications or divisions where one operand is very large. A simple divide-and-conquer algorithm is more effective asymptotically: given a binary number, it is divided by 10k, where k is chosen so that the quotient roughly equals the remainder; then each of these pieces is converted to decimal and the two are concatenated. Given a decimal number, it can be split into two pieces of about the same size, each of which is converted to binary, whereupon the first converted piece is multiplied by 10k and added to the second converted piece, where k is the number of decimal digits in the second, least-significant piece before conversion.

Binary may be converted to and from hexadecimal more easily. This is because the radix of the hexadecimal system (16) is a power of the radix of the binary system (2). More specifically, 16 = 2 ⁴, so it takes four digits of binary to represent one digit of hexadecimal, as shown in the adjacent table.

To convert a hexadecimal number into its binary equivalent, simply substitute the corresponding binary digits:

To convert a binary number into its hexadecimal equivalent, divide it into groups of four bits. If the number of bits isn't a multiple of four, simply insert extra 0 bits at the left (called padding). For example:

To convert a hexadecimal number into its decimal equivalent, multiply the decimal equivalent of each hexadecimal digit by the corresponding power of 16 and add the resulting values:

Binary is also easily converted to the octal numeral system, since octal uses a radix of 8, which is a power of two (namely, 2 ³, so it takes exactly three binary digits to represent an octal digit). The correspondence between octal and binary numerals is the same as for the first eight digits of hexadecimal in the table above. Binary 000 is equivalent to the octal digit 0, binary 111 is equivalent to octal 7, and so forth.

Converting from octal to binary proceeds in the same fashion as it does for hexadecimal:

And from binary to octal:

And from octal to decimal:

Non-integers can be represented by using negative powers, which are set off from the other digits by means of a radix point (called a decimal point in the decimal system). For example, the binary number 11.01 ₂ means:

For a total of 3.25 decimal.

All dyadic rational numbers have a terminating binary numeral-the binary representation has a finite number of terms after the radix point. Other rational numbers have binary representation, but instead of terminating, they recur, with a finite sequence of digits repeating indefinitely. For instance

The phenomenon that the binary representation of any rational is either terminating or recurring also occurs in other radix-based numeral systems. See, for instance, the explanation in decimal. Another similarity is the existence of alternative representations for any terminating representation, relying on the fact that 0.111111... is the sum of the geometric series 2 −1 + 2 −2 + 2 −3 + ... which is 1.

Binary numerals which neither terminate nor recur represent irrational numbers. For instance,

0.10100100010000100000100... does have a pattern, but it is not a fixed-length recurring pattern, so the number is irrational

1.0110101000001001111001100110011111110... is the binary representation of , the square root of 2, another irrational. It has no discernible pattern.

# data[].attributes.attachment_link.description
A binary number is a number expressed in the or binary numeral system, a method of mathematical expression which uses only two symbols: typically "0" ( zero) and "1" ( one). The base-2 numeral system is a positional notation with a radix of 2. Each digit is referred to as a bit, or binary digit.

# data[].attributes.headline
Πως γραφουμε αρνητικους αριθμους στο δυαδικο συστημα

# data[].attributes.subject
Πως γραφουμε αρνητικους αριθμους στο δυαδικο συστημα

# data[].attributes.attachment_link.title
Συμπλήρωμα ως προς 2

# data[].attributes.attachment_link.description
Το συμπλήρωμα ως προς 2 ( Αγγλικά: 2s' complement) ενός δυαδικού αριθμού ορίζεται ως η τιμή που παίρνουμε όταν αντιστρέφουμε όλα τα ψηφία (bits) του δυαδικού αριθμού (αλλάζοντας τα 0 σε 1 και το αντίστροφο - το 0 είναι το συμπλήρωμα του 1 και το αντίθετο) και στην συνέχεια να προσθέσουμε το 1.

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Λογικες πυλες

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Λογικες πυλες

# data[].attributes.body
Οι 7 βασικες πυλες

# data[].attributes.body
για εξασκηση στις λογικές πύλες

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A free, simple, online logic gate simulator. Investigate the behaviour of AND, OR, NOT, NAND, NOR and XOR gates. Select gates from the dropdown list and click "add node" to add more gates. Drag from the hollow circles to the solid circles to make connections. Right click connections to delete them. See below for more detailed instructions.

The demo above allows you to create sequences of logic gates to see how they behave when connected to various inputs and outputs. Initially, you are presented with a simple on/off input and an output. To connect them, click and drag from the hollow circle on the right side of the on/off switch, and release the mouse when you are over the solid circle on the left side of the "output" block.

For each of the logic gates, outputs are hollow circles, and inputs are solid circles. Our "on/off" switch and "output block" aren't actually logic gates, but they are required because they give us the 1s and 0s needed to see how the gates behave. Click the on/off switch and see what happens. It turns yellow. This is our way of differentiating between 0 (off) and 1 (on).

To add a new logic gate, or an additional input or output block, choose from the dropdown menu and then click "add node". The new node will be placed in the top left hand corner, and you can drag it to your desired position. To delete nodes, click the small cross in the top right corner of its enclosing box. To remove connections, you can click on the input (solid circle) and drag away and release, or alternatively you can right click anywhere on the connection.

If you need more space, click on the "Full screen mode" button which will increase the size of the workspace to fill the size of the window. Additionally, you can rename an output by double clicking on its label.

NOT Gate

The NOT gate is also known as an inverter because the output is the exact opposite of the input. It has one input and one output. The two possibilities are written out in the table below. Tables listing all logical possibilities like this are known as truth tables.

AND Gate

The AND gate has two inputs and one output. The output is 1 if both inputs are 1, and for all other cases the output is 0.

NAND Gate

The NAND gate behaves in the opposite fashion to an AND gate. You can think of it as an AND gate followed immediately by a NOT gate. Its output is 0 when the two inputs are 1, and for all other cases, its output is 1. The name NAND comes from joining NOT and AND. The symbol for NAND is the same as that for AND except for the addition of a small circle on the right side.

OR Gate

The OR gate has two inputs and one output. If at least one of the inputs is 1, then the output will be 1. If neither input is 1, the output will be 0.

NOR Gate

Just as the NAND gate could be thought of as an AND followed by a NOT, a NOR can be thought of as an OR also followed by a NOT.

XOR Gate

With an OR gate, if both inputs were 1, the output was 1. However, with an XOR, (exclusive OR), if both inputs are 1, the output is 0. For all other scenarios, the XOR behaves the same as the OR.

Credits

If you've found this educational demo helpful, please consider supporting us on Ko-fi.

Please enable JavaScript to view the comments powered by Disqus.

# data[].attributes.attachment_link.description
A free, simple, online logic gate simulator. Investigate the behaviour of AND, OR, NOT, NAND, NOR and XOR gates. Select gates from the dropdown list and click

# data[].attributes.headline
Λογική Πύλη NOT με διακόπτη και LED

# data[].attributes.subject
Λογική Πύλη NOT με διακόπτη και LED

# data[].attributes.headline
Ποιο είναι το πρόβλημα

# data[].attributes.subject
Ποιο είναι το πρόβλημα

# data[].attributes.body
1. Πως τα ηλεκτρονικά κυκλώματα κάνουν λογικές πράξεις;
2. Πως λειτουργούν οι υπολογιστές;

# data[].attributes.headline
Πρώτο βήμα μας 

# data[].attributes.subject
Πρώτο βήμα μας 

# data[].attributes.body
Προβληματισμός: Σε τι μας είμαι χρήσιμο το "ενα συν ένα ίσον δέκα "

1. Να κατανοήσουμε πως παράγεται λογική από τα κυκλώματα.
2. Να μοιραστούμε τις ανησυχίες μας και τους προβληματισμούς μας με τους συμμαθητές μας.

# data[].attributes.body
Για να δείξουμε πώς τα ηλεκτρονικά κυκλώματα κάνουν λογικές πράξεις θα δημιουργήσουμε απλά κυκλώματα με διακόπτες που θα υλοποιούν λογικές πύλες(and, or, xor, nand ...). Στη συνέχεια θα συνδιάσουμε τις λογικές πύλες για να δημιουργήσουμε έναν ημιαθροιστή και να κάνουμε την πράξη της πρόσθεσης. Τέλος θα δημιουργήσουμε μια αριθμητική λογική μονάδα που θα μπορεί να υλοποιεί περισσότερους υπολογισμούς.

# data[].attributes.headline
Οδηγίες αριθμητική λ

# data[].attributes.body
Οδηγίες αριθμητική λογική μονάδα

# data[].attributes.headline
Αριθμητική λογική μο

# data[].attributes.body
Αριθμητική λογική μονάδα

# data[].attributes.attachment_link.readable_text
In computing, an arithmetic logic unit (ALU) is a combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers.[1][2][3] This is in contrast to a floating-point unit (FPU), which operates on floating point numbers. It is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs).[4]

The inputs to an ALU are the data to be operated on, called operands, and a code indicating the operation to be performed; the ALU's output is the result of the performed operation. In many designs, the ALU also has status inputs or outputs, or both, which convey information about a previous operation or the current operation, respectively, between the ALU and external status registers.

An ALU has a variety of input and output nets, which are the electrical conductors used to convey digital signals between the ALU and external circuitry. When an ALU is operating, external circuits apply signals to the ALU inputs and, in response, the ALU produces and conveys signals to external circuitry via its outputs.

A basic ALU has three parallel data buses consisting of two input operands ( A and B) and a result output ( Y). Each data bus is a group of signals that conveys one binary integer number. Typically, the A, B and Y bus widths (the number of signals comprising each bus) are identical and match the native word size of the external circuitry (e.g., the encapsulating CPU or other processor).

The opcode input is a parallel bus that conveys to the ALU an operation selection code, which is an enumerated value that specifies the desired arithmetic or logic operation to be performed by the ALU. The opcode size (its bus width) determines the maximum number of different operations the ALU can perform; for example, a four-bit opcode can specify up to sixteen different ALU operations. Generally, an ALU opcode is not the same as a machine language opcode, though in some cases it may be directly encoded as a bit field within a machine language opcode.

The status outputs are various individual signals that convey supplemental information about the result of the current ALU operation. General-purpose ALUs commonly have status signals such as:

Carry-out, which conveys the carry resulting from an addition operation, the borrow resulting from a subtraction operation, or the overflow bit resulting from a binary shift operation.

Zero, which indicates all bits of Y are logic zero.

Negative, which indicates the result of an arithmetic operation is negative.

Overflow, which indicates the result of an arithmetic operation has exceeded the numeric range of Y.

Parity, which indicates whether an even or odd number of bits in Y are logic one.

At the end of each ALU operation, the status output signals are usually stored in external registers to make them available for future ALU operations (e.g., to implement multiple-precision arithmetic) or for controlling conditional branching. The collection of bit registers that store the status outputs are often treated as a single, multi-bit register, which is referred to as the "status register" or "condition code register".

The status inputs allow additional information to be made available to the ALU when performing an operation. Typically, this is a single "carry-in" bit that is the stored carry-out from a previous ALU operation.

An ALU is a combinational logic circuit, meaning that its outputs will change asynchronously in response to input changes. In normal operation, stable signals are applied to all of the ALU inputs and, when enough time (known as the " propagation delay") has passed for the signals to propagate through the ALU circuitry, the result of the ALU operation appears at the ALU outputs. The external circuitry connected to the ALU is responsible for ensuring the stability of ALU input signals throughout the operation, and for allowing sufficient time for the signals to propagate through the ALU before sampling the ALU result.

In general, external circuitry controls an ALU by applying signals to its inputs. Typically, the external circuitry employs sequential logic to control the ALU operation, which is paced by a clock signal of a sufficiently low frequency to ensure enough time for the ALU outputs to settle under worst-case conditions.

For example, a CPU begins an ALU addition operation by routing operands from their sources (which are usually registers) to the ALU's operand inputs, while the control unit simultaneously applies a value to the ALU's opcode input, configuring it to perform addition. At the same time, the CPU also routes the ALU result output to a destination register that will receive the sum. The ALU's input signals, which are held stable until the next clock, are allowed to propagate through the ALU and to the destination register while the CPU waits for the next clock. When the next clock arrives, the destination register stores the ALU result and, since the ALU operation has completed, the ALU inputs may be set up for the next ALU operation.

A number of basic arithmetic and bitwise logic functions are commonly supported by ALUs. Basic, general purpose ALUs typically include these operations in their repertoires:[1][2][3][5]

Add: A and B are summed and the sum appears at Y and carry-out.

Add with carry: A, B and carry-in are summed and the sum appears at Y and carry-out.

Subtract: B is subtracted from A (or vice versa) and the difference appears at Y and carry-out. For this function, carry-out is effectively a "borrow" indicator. This operation may also be used to compare the magnitudes of A and B; in such cases the Y output may be ignored by the processor, which is only interested in the status bits (particularly zero and negative) that result from the operation.

Subtract with borrow: B is subtracted from A (or vice versa) with borrow (carry-in) and the difference appears at Y and carry-out (borrow out).

Two's complement (negate): A (or B) is subtracted from zero and the difference appears at Y.

Increment: A (or B) is increased by one and the resulting value appears at Y.

Decrement: A (or B) is decreased by one and the resulting value appears at Y.

Pass through: all bits of A (or B) appear unmodified at Y. This operation is typically used to determine the parity of the operand or whether it is zero or negative, or to load the operand into a processor register.

AND: the bitwise AND of A and B appears at Y.

OR: the bitwise OR of A and B appears at Y.

Exclusive-OR: the bitwise XOR of A and B appears at Y.

Ones' complement: all bits of A (or B) are inverted and appear at Y.

Type

Left

Right

ALU shift operations cause operand A (or B) to shift left or right (depending on the opcode) and the shifted operand appears at Y. Simple ALUs typically can shift the operand by only one bit position, whereas more complex ALUs employ barrel shifters that allow them to shift the operand by an arbitrary number of bits in one operation. In all single-bit shift operations, the bit shifted out of the operand appears on carry-out; the value of the bit shifted into the operand depends on the type of shift.

Arithmetic shift: the operand is treated as a two's complement integer, meaning that the most significant bit is a "sign" bit and is preserved.

Logical shift: a logic zero is shifted into the operand. This is used to shift unsigned integers.

Rotate: the operand is treated as a circular buffer of bits so its least and most significant bits are effectively adjacent.

Rotate through carry: the carry bit and operand are collectively treated as a circular buffer of bits.

In integer arithmetic computations, multiple-precision arithmetic is an algorithm that operates on integers which are larger than the ALU word size. To do this, the algorithm treats each operand as an ordered collection of ALU-size fragments, arranged from most-significant (MS) to least-significant (LS) or vice versa. For example, in the case of an 8-bit ALU, the 24-bit integer 0x123456 would be treated as a collection of three 8-bit fragments: 0x12 (MS), 0x34, and 0x56 (LS). Since the size of a fragment exactly matches the ALU word size, the ALU can directly operate on this "piece" of operand.

The algorithm uses the ALU to directly operate on particular operand fragments and thus generate a corresponding fragment (a "partial") of the multi-precision result. Each partial, when generated, is written to an associated region of storage that has been designated for the multiple-precision result. This process is repeated for all operand fragments so as to generate a complete collection of partials, which is the result of the multiple-precision operation.

In arithmetic operations (e.g., addition, subtraction), the algorithm starts by invoking an ALU operation on the operands' LS fragments, thereby producing both a LS partial and a carry out bit. The algorithm writes the partial to designated storage, whereas the processor's state machine typically stores the carry out bit to an ALU status register. The algorithm then advances to the next fragment of each operand's collection and invokes an ALU operation on these fragments along with the stored carry bit from the previous ALU operation, thus producing another (more significant) partial and a carry out bit. As before, the carry bit is stored to the status register and the partial is written to designated storage. This process repeats until all operand fragments have been processed, resulting in a complete collection of partials in storage, which comprise the multi-precision arithmetic result.

In multiple-precision shift operations, the order of operand fragment processing depends on the shift direction. In left-shift operations, fragments are processed LS first because the LS bit of each partial-which is conveyed via the stored carry bit-must be obtained from the MS bit of the previously left-shifted, less-significant operand. Conversely, operands are processed MS first in right-shift operations because the MS bit of each partial must be obtained from the LS bit of the previously right-shifted, more-significant operand.

In bitwise logical operations (e.g., logical AND, logical OR), the operand fragments may be processed in any arbitrary order because each partial depends only on the corresponding operand fragments (the stored carry bit from the previous ALU operation is ignored).

Although an ALU can be designed to perform complex functions, the resulting higher circuit complexity, cost, power consumption and larger size makes this impractical in many cases. Consequently, ALUs are often limited to simple functions that can be executed at very high speeds (i.e., very short propagation delays), and the external processor circuitry is responsible for performing complex functions by orchestrating a sequence of simpler ALU operations.

For example, computing the square root of a number might be implemented in various ways, depending on ALU complexity:

Calculation in a single clock: a very complex ALU that calculates a square root in one operation.

Calculation pipeline: a group of simple ALUs that calculates a square root in stages, with intermediate results passing through ALUs arranged like a factory production line. This circuit can accept new operands before finishing the previous ones and produces results as fast as the very complex ALU, though the results are delayed by the sum of the propagation delays of the ALU stages. For more information, see the article on instruction pipelining.

Iterative calculation: a simple ALU that calculates the square root through several steps under the direction of a control unit.

The implementations above transition from fastest and most expensive to slowest and least costly. The square root is calculated in all cases, but processors with simple ALUs will take longer to perform the calculation because multiple ALU operations must be performed.

An ALU is usually implemented either as a stand-alone integrated circuit (IC), such as the 74181, or as part of a more complex IC. In the latter case, an ALU is typically instantiated by synthesizing it from a description written in VHDL, Verilog or some other hardware description language. For example, the following VHDL code describes a very simple 8-bit ALU:

entity alu is
port (  -- the alu connections to external circuitry:
  A  : in signed ( 7 downto 0 );   -- operand A
  B  : in signed ( 7 downto 0 );   -- operand B
  OP : in unsigned ( 2 downto 0 ); -- opcode
  Y  : out signed ( 7 downto 0 ));  -- operation result
end alu ;

architecture behavioral of alu is
begin
 case OP is  -- decode the opcode and perform the operation:
 when "000" =>  Y <= A + B ;   -- add
 when "001" =>  Y <= A - B ;   -- subtract
 when "010" =>  Y <= A - 1 ;   -- decrement
 when "011" =>  Y <= A + 1 ;   -- increment
 when "100" =>  Y <= not A ;   -- 1's complement
 when "101" =>  Y <= A and B ; -- bitwise AND
 when "110" =>  Y <= A or B ;  -- bitwise OR
 when "111" =>  Y <= A xor B ; -- bitwise XOR
 when others => Y <= ( others => 'X' );
 end case ;
end behavioral ;

Mathematician John von Neumann proposed the ALU concept in 1945 in a report on the foundations for a new computer called the EDVAC.[6]

The cost, size, and power consumption of electronic circuitry was relatively high throughout the infancy of the information age. Consequently, all serial computers and many early computers, such as the PDP-8, had a simple ALU that operated on one data bit at a time, although they often presented a wider word size to programmers. One of the earliest computers to have multiple discrete single-bit ALU circuits was the 1948 Whirlwind I, which employed sixteen of such "math units" to enable it to operate on 16-bit words.

In 1967, Fairchild introduced the first ALU implemented as an integrated circuit, the Fairchild 3800, consisting of an eight-bit ALU with accumulator.[7] Other integrated-circuit ALUs soon emerged, including four-bit ALUs such as the Am2901 and 74181. These devices were typically " bit slice" capable, meaning they had "carry look ahead" signals that facilitated the use of multiple interconnected ALU chips to create an ALU with a wider word size. These devices quickly became popular and were widely used in bit-slice minicomputers.

Microprocessors began to appear in the early 1970s. Even though transistors had become smaller, there was often insufficient die space for a full-word-width ALU and, as a result, some early microprocessors employed a narrow ALU that required multiple cycles per machine language instruction. Examples of this includes the popular Zilog Z80, which performed eight-bit additions with a four-bit ALU.[8] Over time, transistor geometries shrank further, following Moore's law, and it became feasible to build wider ALUs on microprocessors.

Modern integrated circuit (IC) transistors are orders of magnitude smaller than those of the early microprocessors, making it possible to fit highly complex ALUs on ICs. Today, many modern ALUs have wide word widths, and architectural enhancements such as barrel shifters and binary multipliers that allow them to perform, in a single clock cycle, operations that would have required multiple operations on earlier ALUs.

ALUs can be realized as mechanical, electro-mechanical or electronic circuits[9][failed verification ] and, in recent years, research into biological ALUs has been carried out[10][11] (e.g., actin-based).[12]

1. ^ A.P.Godse; D.A.Godse (2009). "3". Digital Logic Design. Technical Publications. pp. 9-3. ISBN 978-81-8431-738-1.

2. ^ Leadership Education and Training (LET) 2: Programmed Text. Headquarters, Department of the Army. 2001. pp. 371-.

3. ^ A.P.Godse; D.A.Godse (2009). "Appendix". Digital Logic Circuits. Technical Publications. pp. C-1. ISBN 978-81-8431-650-6.

4. ^ "1. An Introduction to Computer Architecture - Designing Embedded Hardware, 2nd Edition [Book]". www.oreilly.com.

5. ^ Horowitz, Paul; Winfield Hill (1989). "14.1.1". The Art of Electronics (2nd ed.). Cambridge University Press. pp. 990-. ISBN 978-0-521-37095-0.

6. ^ Philip Levis (November 8, 2004). ("Jonathan von Neumann and EDVAC" (PDF). cs.berkeley.edu. pp. 1, 3. Archived from the original PDF) on September 23, 2015.

7. ^ Lee Boysel (2007-10-12). "Making Your First Million (and other tips for aspiring entrepreneurs)". U. Mich. EECS Presentation / ECE Recordings. Archived from the original on 2012-11-15.

8. Ken Shirriff. ^ "The Z-80 has a 4-bit ALU. Here's how it works." 2013, righto.com

9. ^ Reif, John H. (2009), Meyers, Robert A. (ed.), "Mechanical Computing: The Computational Complexity of Physical Devices", Encyclopedia of Complexity and Systems Science, New York, NY: Springer, pp. 5466-5482, doi:10.1007/978-0-387-30440-3_325, ISBN 978-0-387-30440-3

10. ^ Lin, Chun-Liang; Kuo, Ting-Yu; Li, Wei-Xian (2018-08-14). "Synthesis of control unit for future biocomputer". Journal of Biological Engineering. 12 (1): 14. doi:10.1186/s13036-018-0109-4. ISSN 1754-1611. PMC 6092829. PMID 30127848.

11. ^ Gerd Hg Moe-Behrens. "The biological microprocessor, or how to build a computer with biological parts".

12. ^ Das, Biplab; Paul, Avijit Kumar; De, Debashis (2019-08-16). "An unconventional Arithmetic Logic Unit design and computing in Actin Quantum Cellular Automata". Microsystem Technologies. doi:10.1007/s00542-019-04590-1. ISSN 1432-1858.

# data[].attributes.attachment_link.description
In computing, an arithmetic logic unit (ALU) is a combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers.[1] [2] [3] This is in contrast to a floating-point unit (FPU), which operates on floating point numbers.

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Ποια είναι τα κριτήρια αξιολόγησης

# data[].attributes.subject
Ποια είναι τα κριτήρια αξιολόγησης

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Σαφής προσδιορισμός προβλήματος: 20%

Επίλυση προβλήματος: 30%

Χρήση νέων τεχνολογιών: 30%

Συνεργασία με τοπικούς φορείς: 10%

Παρουσίαση: 10%

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Πώς καταθέτω τη περιγραφή της ιδέας και της κατασκευής της ομάδας στο διαγωνισμό;

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Πώς καταθέτω τη περιγραφή της ιδέας και της κατασκευής της ομάδας στο διαγωνισμό;

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Για την κατάθεση της ιδέας και κατασκευής, ο υπεύθυνος καθηγητής/εκπαιδευτής της ομάδας πρέπει να συμπληρώσει ηλεκτρονικά μια επιπλέον φόρμα, ως συνέχεια της δήλωσης συμμετοχής της ομάδας, που αφορά αποκλειστικά στην κατασκευή, απαντώντας με την ομάδα στα παρακάτω:

Ποιο είναι το πρόβλημα, ζήτημα ή πρόκληση που αντιμετωπίζετε στην τοπική σας κοινότητα ή την καθημερινή σας ζωή και θα σας απασχολήσει στο πλαίσιο του διαγωνισμού Generation Next; (έως 200 λέξεις)

Ποια είναι η ιδέα μέσω της οποίας θα εφαρμόσετε το STEM και τις εκθετικές τεχνολογίες για να αντιμετωπιστεί το εν λόγω πρόβλημα, ζήτημα ή πρόκληση; (έως 200 λέξεις)

Ποια/ες τεχνολογίες χρησιμοποιήσατε για τη δημιουργία της κατασκευής σας; (έως 200 λέξεις)

Ποιος είναι ο αντίκτυπος στην κοινότητα από την προτεινόμενη λύση ή κατασκευή; (έως 200 λέξεις)

Περιγράψτε αν ήρθατε σε επικοινωνία με τοπικούς φορείς (δήμο, εταιρείες, ερευνητικά κέντρα πανεπιστήμια, οργανισμούς) τόσο για τον εντοπισμό του προβλήματος και την ανάπτυξη της προτεινόμενης λύσης, όσο και για πιθανές μελλοντικές συνέργειες. (έως 200 λέξεις)

Περιγράψτε την ομάδα μαθητών, τον τρόπο συνεργασίας και την ανάθεση ρόλων. (έως 200 λέξεις)

Επιπροσθέτως, οι ομάδες καλούνται να αναρτήσουν βίντεο (στα ελληνικά) με διάρκεια από ένα (1) έως τρία (3) λεπτά. Το βίντεο θα πρέπει να παρουσιάζει την ομάδα, το επιλεγμένο πρόβλημα, τη  προτεινόμενη λύση και την κατασκευή/εφαρμογή σε λειτουργία. H συμμετοχή θα πρέπει να συμπληρωθεί και με την ανάρτηση ξεχωριστών φωτογραφιών της ομάδας και της κατασκευής.

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Παζούλης Παναγιώτης (Εκπαιδευτικός)
Ορφανίδης Κωνσταντίνος
Παπαδοπούλου Αικατερίνη
Ορφανίδου Ελένη