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Onsemi wafer (silicone) variations;

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pre-damage the component

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Source contact depth control

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Trench misalignment

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Source contact width

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A Reverse és a Battery FET-es külön kezelni. Reverse FET esetlén mechanika hiba?

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Doping process

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sample based probe test (not 100%)

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Gate trench impurities

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Vehicle network and other ECUs behave in a way that is harmful to our ECU

The test vehicle we use is not representative/production intent

The vehicle SW is not up-to-date (including the SW of other ECUs involved)

Charging the vehicle 12 V battery

High frequency ripple 1kHz, caused by battery charger

DC/DC converter interaction with EPS

Charging the 400 V battery

High amplitude voltage fluctuations with high dV/dt

High freq EM fields

A and B sides are always connected? Ground shift?

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sample based AOI inspection (KLA, not 100%)

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Wafer vendor validation

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DC link cap charging causes unstented stress

Maybe a small fraction of the FETs die is doing the heavy lifting, causing thermal overstress, degradation of the oxide layer

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A FET kialakítása miatt nem képes a lavina áramok elviselésére.

Ez a FET illik-e abba a működési környezetbe, ahol használjuk.

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Valamelyik gyártástechnológiai lépés során elszenvedett hatás miatt nem képes a lavina áramok elviselésére.

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Only 3 mm exclusion from wafer edge

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No effective knowlegde transfer from Aizu to EFK

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Potentially high allowed solder void ratio

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Particle

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5C vs CCC összehasolítása

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Masking failure - due to recognized pattern of failure locations

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Not 100% DPAT at probe test (10% smart sample) --> DPAT is to identify and exclude outliers

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Structural (physical) limitation of trench MOSFET design

ONSEMI simulation of the trenches with basic smaller mosfets had the same failure position

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5C működési tartománya - kondíciók meg voltak erősítve ONSEMI által ?

repetitive avalanche? ( a datasheet jellemzően single avalanche-ra vonatkozik)

design review?