# data[].attributes.headline
New memory transistor integrates photocrosslinker into molecular switches to adjust its threshold voltage

# data[].attributes.subject
New memory transistor integrates photocrosslinker into molecular switches to adjust its threshold voltage

# data[].attributes.body
En el articulo se explica el desarrollo de un nuevo transistor de memoria que ajusta su voltaje umbral mediante la integración de un fotocruzador en interruptores moleculares. Esto permite una conmutación precisa y estable de la capa semiconductora, mejorando el rendimiento y la durabilidad del transistor. Este desarrollo es importante para la evolución de la microelectrónica, ofreciendo nuevas posibilidades para el almacenamiento y procesamiento de datos de alta eficiencia

Andres Mateo Chilito Avella :)

# data[].attributes.attachment_link.readable_text
A. F8T2 polymer employed in tandem with the molecular framework of a molecular switch including a photocrosslinker. Credit: POSTECH

A research team has developed a memory transistor capable of adjusting its threshold voltage. This innovation combines two molecules that form a stable bond with a polymeric semiconductor, situated at the end of a molecular switch. The research was recently featured in the online edition of Advanced Science.

These molecular switches control electrical signals by leveraging the conversion properties of diverse organic molecular isomers. When integrated into field-effect transistors (FETs), they govern electron flow at the molecular scale.

While molecular switch-based FETs have been a key technology for implementing organic FETs (OFETs) in recent years, their longevity has been hampered by the limited ability of the molecules that act as switch molecules to serve as efficient deep traps for capturing and storing electrons within the semiconductor layer.

In this research, the team tackled this challenge by constructing a bridge illuminated by "light." They pioneered a novel method to establish a "photonic bridge," a light-triggered chemical linkage between a molecular switch molecule and a polymeric organic semiconductor.

At the terminus of the molecular switch, consisting of diarylethene (DAE), the team combined an azide and a diazirine. Under light exposure, these two functional groups forge a chemical connection with the organic polymer semiconductor, stabilizing the typically precarious closed isomer of DAE in a deep-trapped state.

In experimental trials, the OFETs incorporating the team's DAE compounds demonstrated remarkable endurance, maintaining stable deep-trap states for durations exceeding a million seconds. Furthermore, they showcased exceptional photoprogrammable on-off switching ratios surpassing 1,000 at a voltage of 22 V, alongside outstanding storage performance, enduring stability through more than 100 cycles.

Specifically, the team's OFETs boast precise patterning through photocrosslinking, enabling meticulous control of the semiconductor layer's structure. The researchers identified diverse applications for their findings, spanning microelectronics and optoelectronics.

The research team was led by Professor Dae Sung Chung and Dr. Syed Zahid Hassan from the Department of Chemical Engineering at Pohang University of Science and Technology (POSTECH). Professor Chung said, "This research unveils fresh prospects in memory transistor realms, impacting data storage and processing technologies profoundly. It holds promise for innovation across a spectrum of disciplines, extending beyond the domain of transistors."

More information: Syed Zahid Hassan et al, Photophore‐Anchored Molecular Switch for High‐Performance Nonvolatile Organic Memory Transistor, Advanced Science (2024). DOI: 10.1002/advs.202401482

# data[].attributes.attachment_link.title
New memory transistor integrates photocrosslinker into molecular switches to adjust its threshold voltage

# data[].attributes.attachment_link.description
A research team has developed a memory transistor capable of adjusting its threshold voltage. This innovation combines two molecules that form a stable bond with a polymeric semiconductor, situated at the end of a molecular switch. The research was recently featured in the online edition of Advanced Science.

# data[].attributes.headline
Advancing transistor technology with triply-degenerate semimetal PtBi₂

# data[].attributes.subject
Advancing transistor technology with triply-degenerate semimetal PtBi₂

# data[].attributes.body
En el artículo se observa cómo han utilizado el semimetal triplemente degenerado PtBi₂ como capa de contacto entre electrodos de oro y el semiconductor WS₂, mejorando significativamente el rendimiento del transistor. Alcanzaron una relación de conmutación superior a 10^6 y una movilidad media de 85 cm²V⁻¹s⁻¹. Este es un avance en la tecnología de transistores increíble en general para la fabricación de dispositivos electrónicos mucho más rápidos y eficientes, integrando nuevos materiales semimetálicos

Andres Mateo Chilito Avella :)

# data[].attributes.attachment_link.readable_text
PtBi2 work as contact layer in WS2 transistor. Credit: Prof. Shenghuang Lin from Songshan Lake Materials Laboratory

Despite its promising characteristics in condensed matter physics, the triply-degenerate semimetal PtBi ₂ has been largely unexplored in practical applications, particularly in semiconductor technology. The main difficulties include a lack of empirical data on the integration of PtBi ₂ with existing semiconductor components and the need for innovative approaches to leverage its unique properties, such as high stability and mobility, within the constraints of current electronic manufacturing processes.

Addressing these challenges could unlock new possibilities in transistor design and broader semiconductor applications, making it crucial to explore the practical applicability of PtBi ₂ in real-world electronics.

A research team from Songshan Lake Materials laboratory successfully used PtBi ₂ flakes as interlayer contact between metal electrodes (Au) and WS ₂, a widely studied semiconductor. This method significantly enhanced the transistor performance, achieving a switching ratio above 10 ⁶ and an average mobility of 85 cm²V⁻¹s⁻¹, thus meeting and potentially exceeding the stringent demands of integrated circuit applications.

The work is published in the journal Materials Futures.

Future research is poised to explore diverse PtBi ₂-based device architectures, focusing on optimizing the interplay between device miniaturization and enhanced performance. Given its promising electronic properties, application of PtBi ₂ could extend beyond traditional transistors to optoelectronic and spintronic devices.

"PtBi ₂ stands out due to its unique electronic structure, exceptional air stability and ability to facilitate van der Waals contacts, which simplifies the device fabrication process and leads to stable, long-term device performance," explained Prof. Lin, one of the lead researchers of the study.

"This material not only reduces the Schottky barrier, which is a common challenge in transistor technology but also avoids the Fermi pinning effect that occurs during metal deposition."

One of the most notable aspects of the study is the use of a non-destructive van der Waals transfer technique, which maintains the integrity of the materials and interfaces. The researchers believe this method will offer a novel path to integrate new materials into semiconductor technology.

The findings are expected to have broad implications for the semiconductor industry, providing a new material platform for developing more energy-efficient electronic devices with high functionality. The team is optimistic about the future applications of PtBi ₂, not only in transistors but also in optoelectronic and spintronic devices.

More information: Bohan Wei et al, Triply Degenerate Semimetal PtBi2 as van der Waals Contact interlayer in Two-Dimensional Transistor, Materials Futures (2024). DOI: 10.1088/2752-5724/ad47cf

Provided by Songshan Lake Materials Laboratory

# data[].attributes.attachment_link.title
Advancing transistor technology with triply-degenerate semimetal PtBi₂

# data[].attributes.attachment_link.description
Despite its promising characteristics in condensed matter physics, the triply-degenerate semimetal PtBi2 has been largely unexplored in practical applications, particularly in semiconductor technology. The main difficulties include a lack of empirical data on the integration of PtBi2 with existing semiconductor components and the need for innovative approaches to leverage its unique properties, such as high stability and mobility, within the constraints of current electronic manufacturing processes.

# data[].attributes.headline
Tweaking isotopes sheds light on promising approach to engineer semiconductors

# data[].attributes.subject
Tweaking isotopes sheds light on promising approach to engineer semiconductors

# data[].attributes.body
En el Laboratorio Nacional de Oak Ridge demostraron que pequeños cambios en el contenido isotópico de materiales semiconductores delgados influyen en sus propiedades ópticas y electrónicas. Utilizando cristales de disulfuro de molibdeno, observaron cambios en la estructura electrónica y el espectro óptico, esto nos abre muchas oportunidades para el diseño de dispositivos semiconductores mediante la ingeniería de isótopos, lo que puede revolucionar dispositivos en microelectrónica, células solares, etc.

Andres Mateo Chilito Avella :)

# data[].attributes.attachment_link.readable_text
Research led by scientists at the Department of Energy's Oak Ridge National Laboratory has demonstrated that small changes in the isotopic content of thin semiconductor materials can influence their optical and electronic properties, possibly opening the way to new and advanced designs with the semiconductors.

Partly because of semiconductors, electronic devices and systems become more advanced and sophisticated every day. That's why for decades researchers have studied ways to improve semiconductor compounds to influence how they carry electrical current. One approach is to use isotopes to change the physical, chemical and technological properties of materials.

Isotopes are members of a family of an element that all have the same number of protons but different numbers of neutrons and thus different masses. Isotope engineering has traditionally focused on enhancing so-called bulk materials that have uniform properties in three dimensions, or 3D. But new research led by ORNL has advanced the frontier of isotope engineering where current is confined in two dimensions, or 2D, inside flat crystals and where a layer is only a few atoms thick. The 2D materials are promising because their ultrathin nature could allow for precise control over their electronic properties.

"We observed a surprising isotope effect in the optoelectronic properties of a single layer of molybdenum disulfide when we substituted a heavier isotope of molybdenum in the crystal, an effect that opens opportunities to engineer 2D optoelectronic devices for microelectronics, solar cells, photodetectors and even next-generation computing technologies," said ORNL scientist Kai Xiao.

Yiling Yu, a member of Xiao's research team, grew isotopically pure 2D crystals of atomically thin molybdenum disulfide using molybdenum atoms of different masses. Yu noticed small shifts in the color of light emitted by the crystals under photoexcitation, or stimulation by light.

"Unexpectedly, the light from the molybdenum disulfide with the heavier molybdenum atoms was shifted farther to the red end of the spectrum, which is opposite to the shift one would expect for bulk materials," Xiao said. The red shift indicates a change in the electronic structure or optical properties of the material.

Xiao and the team, working with theorists Volodymyr Turkowski and Talat Rahman at the University of Central Florida, knew that the phonons, or crystal vibrations, must be scattering the excitons, or optical excitations, in unexpected ways in the confined dimensions of these ultrathin crystals. They discovered how this scattering shifts the optical bandgap to the red end of the light spectrum for heavier isotopes. "Optical bandgap" refers to the minimum amount of energy needed to make a material absorb or emit light. By adjusting the bandgap, researchers can make semiconductors absorb or emit different colors of light, and such tunability is essential for designing new devices.

ORNL's Alex Puretzky described how different crystals grown on a substrate can show small shifts in emitted color caused by regional strain in the substrate. To prove the anomalous isotope effect and measure its magnitude to compare with theoretical predictions, Yu grew molybdenum disulfide crystals with two molybdenum isotopes in one crystal.

"Our work was unprecedented in that we synthesized a 2D material with two isotopes of the same element but with different masses, and we joined the isotopes laterally in a controlled and gradual manner in a single monolayer crystal," Xiao said. "This enabled us to observe the intrinsic anomalous isotope effect on the optical properties in the 2D material without the interference caused by an inhomogeneous sample."

The study demonstrated that even a small change of isotope masses in the atomically thin 2D semiconductor materials can influence optical and electronic properties -- a finding that provides an important basis for continued research.

"Previously, the belief was that to make devices such as photovoltaics and photodetectors, we had to combine two different semiconductor materials to make junctions to trap excitons and separate their charges. But actually, we can use the same material and just change its isotopes to create isotopic junctions to trap the excitons," Xiao said. "This research also tells us that through isotope engineering, we can tune the optical and electronic properties to design new applications."

For future experiments, Xiao and the team plan to collaborate with the experts at the High Flux Isotope Reactor and the Isotope Science and Engineering Directorate at ORNL. These facilities can provide various highly enriched isotope precursors to grow different isotopically pure 2D materials. The team can then further investigate the isotope effect on spin properties for their application in spin electronics and quantum emission.

This work was supported by DOE's Office of Science, Basic Energy Sciences, Materials Sciences and Engineering Division and was performed at the Center for Nanophase Materials Sciences, or CNMS, at ORNL, an Office of Science user facility. The CNMS supported the TOF-SIMS, STEM and optical spectroscopy measurements.

# data[].attributes.attachment_link.keywords[]
materials science; optics; electronics; engineering and construction; spintronics research; robotics; computer science; math puzzles

# data[].attributes.attachment_link.title
Tweaking isotopes sheds light on promising approach to engineer semiconductors

# data[].attributes.attachment_link.description
Scientists have demonstrated that small changes in the isotopic content of thin semiconductor materials can influence their optical and electronic properties, possibly opening the way to new and advanced designs with the semiconductors.

# data[].attributes.headline
Research demonstrates high qubit control fidelity and uniformity in single-electron control

# data[].attributes.subject
Research demonstrates high qubit control fidelity and uniformity in single-electron control

# data[].attributes.body
Investigadores de Intel lograron una alta uniformidad en el control de qubits de espín de electrones individuales, esto es vital para escalar procesadores cuánticos basados en silicio. Utilizando un proceso de prueba criogénica de 300 milímetros y técnicas de fabricación CMOS, demostraron un gate del 99.9%. Este avance es asombroso porque permite densidades de qubits super altas y un mejor rendimiento, impulsando el desarrollo de computadoras cuánticas tolerantes a fallos. Sabemos que la uniformidad en los qubits es esenciales para construir sistemas cuánticos escalables, con el potencial de revolucionar campos como la criptografía o la ciencia de materiales.

Andres Mateo Chilito Avella :)

# data[].attributes.attachment_link.readable_text
A 300-millimeter Intel silicon spin qubit wafer. In May 2024, Nature published an Intel research paper, "Probing single electrons across 300-mm spin qubit wafers," demonstrating state-of-the-art uniformity, fidelity and measurement statistics of spin qubits. Credit: Intel Corporation

The journal Nature has published a research paper, " Probing single electrons across 300-mm spin qubit wafers," demonstrating state-of-the-art uniformity, fidelity and measurement statistics of spin qubits. The industry-leading research opens the door for the mass production and continued scaling of silicon-based quantum processors, all of which are requirements for building a fault-tolerant quantum computer.

Quantum hardware researchers from Intel developed a 300-millimeter cryogenic probing process to collect high-volume data on the performance of spin qubit devices across whole wafers using complementary metal oxide semiconductor (CMOS) manufacturing techniques.

The improvements to qubit device yield combined with the high-throughput testing process enabled researchers to obtain significantly more data to analyze uniformity, an important step needed to scale up quantum computers. Researchers also found that single-electron devices from these wafers perform well when operated as spin qubits, achieving 99.9% gate fidelity. This fidelity is the highest reported for qubits made with all-CMOS-industry manufacturing.

The small size of spin qubits, measuring about 100 nanometers across, makes them denser than other qubit types (e.g., superconducting), enabling more complex quantum computers to be made on a single chip of the same size. The fabrication approach was conducted using extreme ultraviolet (EUV) lithography, which allowed Intel to achieve these tight dimensions while also manufacturing in high volume.

Realizing fault-tolerant quantum computers with millions of uniform qubits will require highly reliable fabrication processes. Drawing upon its legacy in transistor manufacturing expertise, Intel is at the forefront of creating silicon spin qubits similar to transistors by leveraging its cutting-edge 300-millimeter CMOS manufacturing techniques, which routinely produce billions of transistors per chip.

Building on these findings, Intel plans to continue to make advances in using these techniques to add more interconnect layers to fabricate 2D arrays with increased qubit count and connectivity, as well as demonstrating high-fidelity two- qubit gates on its industry manufacturing process. However, the main priority will continue to be scaling quantum devices and improving performance with its next generation quantum chip.

More information: Samuel Neyens et al, Probing single electrons across 300-mm spin qubit wafers, Nature (2024). DOI: 10.1038/s41586-024-07275-6

# data[].attributes.attachment_link.title
Research demonstrates high qubit control fidelity and uniformity in single-electron control

# data[].attributes.attachment_link.description
The journal Nature has published a research paper, "Probing single electrons across 300-mm spin qubit wafers," demonstrating state-of-the-art uniformity, fidelity and measurement statistics of spin qubits. The industry-leading research opens the door for the mass production and continued scaling of silicon-based quantum processors, all of which are requirements for building a fault-tolerant quantum computer.

# data[].attributes.headline
conecta los chips semiconductores con la industria: 400 expositores y 250 expertos abordan los desafíos que enfrentan muchas industrias

# data[].attributes.subject
conecta los chips semiconductores con la industria: 400 expositores y 250 expertos abordan los desafíos que enfrentan muchas industrias

# data[].attributes.body
El artículo presenta el IOT Solutions World Congress (IOTSWC) como un evento internacional clave que destaca la importancia de los semiconductores en la transformación de la industria hacia el Internet de las Cosas (IoT) y la Cuarta Revolución Industrial. Los semiconductores, elementos esenciales en la fabricación de dispositivos electrónicos como ordenadores, smartphones y coches, son destacados por su papel crítico en la implementación de tecnologías disruptivas. Este enfoque se relaciona directamente con la carrera de ingeniería electrónica, ya que los ingenieros electrónicos son los encargados de diseñar, desarrollar y mejorar los sistemas y dispositivos electrónicos, incluidos los circuitos integrados y los chips semiconductores, que son la base de la innovación tecnológica en la actualidad.

Además, el artículo destaca la iniciativa de la Generalitat de Cataluña para impulsar la industria de semiconductores en la región, subrayando el compromiso con el desarrollo y la promoción de la ingeniería electrónica a nivel local y global. Esta estrategia implica la colaboración entre empresas, agencias gubernamentales y agentes de investigación e innovación, lo que refuerza la importancia de la ingeniería electrónica como motor de la economía y el progreso tecnológico. En resumen, el artículo resalta la relevancia de los semiconductores en la ingeniería electrónica y cómo eventos como el IOTSWC y las iniciativas gubernamentales pueden influir en el campo y en el desarrollo profesional de los ingenieros electrónicos.

Veronica Garcia Castro

# data[].attributes.attachment_link.readable_text
La próxima edición del IOT Solutions World Congress, que tendrá lugar del 21 al 23 de mayo en el recinto de Gran Via de Fira de Barcelona, ​​reunirá a un número importante de fabricantes de chips semiconductores que mostrarán sus proyectos y productos que serán clave para el salto hacia la digitalización y modernización de la industria.

‍

En esta línea, la Generalitat, consciente del papel vital que desempeñan los semiconductores en la industria actual y con el objetivo de impulsar este sector en Cataluña, agrupará en un único stand en IOT Solutions World Congress a un gran número de empresas que operan en este campo en Cataluña. Estos negocios se suman a la oferta de otras firmas internacionales como ST Microelectronics, Lacroix, Qualcomm, Tessolve o Würth Elektronik, que mostrarán sus proyectos e iniciativas en el campo de los semiconductores.

‍

Con esta iniciativa, el certamen contribuye a impulsar la estrategia desarrollada por la Generalitat de Cataluña para impulsar la industria de semiconductores y que ha dado lugar a la creación de la Alianza Catalana de Semiconductores, una iniciativa integrada por varios ministerios de la Generalitat, empresas y agentes de investigación e innovación, que trabajarán juntos para consolidar Cataluña como un hub líder en semiconductores en Europa.

‍

El director del salón, Marc Tarragó, afirmó que "IOTSWC ofrece a los fabricantes de chips una oportunidad de llegar a nuevos clientes nacionales e internacionales en un momento clave para la transformación de la industria" . Asimismo, señaló: "queríamos darle un impulso a este segmento, que está ganando protagonismo en una edición que también se consolida como el evento líder a nivel mundial para impulsar la Cuarta Revolución Industrial".

‍

Por su parte, el secretario general de Empresa y Competitividad y director general de ACCIÓ, Albert Castellanos i Maduell, señaló que "Cataluña es uno de los principales centros de atracción tecnológica de Europa, por número de empresas, talento y capacidad de conectar sectores de todo el tejido económico" . En este sentido, ha añadido, "el Gobierno catalán apuesta por una estrategia de impulso de industrias como la de los semiconductores, y por la internacionalización y consolidación de las empresas catalanas que forman parte de ellas, como vector estratégico y transformador de nuestra industria".

‍

Según datos de la Semiconductor Industry Association (SIA), el mercado global de semiconductores alcanzará los 490.977 millones de euros en 2023, un 8% menos que en 2022, siendo Taiwán el mayor productor mundial de chips con el 60% de las ventas, superando a Estados Unidos. y China.

‍

Organizado por Fira de Barcelona, ​​IOTSWC 2024 espera reunir a 12.000 visitantes de más de 100 países, más de 400 expositores y un cartel de 250 ponentes y expertos que participarán en 125 sesiones del congreso.

‍

El evento contará con cuatro áreas -Congreso, Área de Exposición, Actividades y Seguridad y Ciberseguridad- y ofrecerá una plataforma de innovación centrada en el intercambio de conocimiento, tendencias disruptivas y soluciones aplicables.

‍

# data[].attributes.attachment_link.title
Intelectium > El Congreso Mundial de Soluciones IOT 2024 conecta los chips semiconductores con la industria

# data[].attributes.attachment_link.description
400 expositores y 250 expertos abordan los desafíos que enfrentan muchas industrias

# data[].attributes.headline
Apple quiere desarrollar el primer chip de 2 nanómetros y estrenarlo con el iPhone 17, según reporte

# data[].attributes.subject
Apple quiere desarrollar el primer chip de 2 nanómetros y estrenarlo con el iPhone 17, según reporte

# data[].attributes.body
Apple será el primer cliente de TSMC en recibir microprocesadores de 2nm. El rendimiento del iPhone 17 podría mejorar entre 10 y 15% en comparación con el iPhone 15 Pro.

El artículo se centra en los avances tecnológicos en el campo de los semiconductores, específicamente en la carrera por desarrollar chips de 2 nanómetros (nm), liderada por Apple en colaboración con Taiwan Semiconductor Manufacturing Company Limited (TSMC). Se destaca cómo la reducción del tamaño de los transistores en los chips permite mejorar el rendimiento de los dispositivos electrónicos, como los smartphones, al integrar más transistores y aumentar la potencia y la eficiencia energética. Además, se menciona la estrategia de Apple de buscar independencia en el desarrollo de chips personalizados, como el M1 para sus computadoras, y la incursión en el mercado de la inteligencia artificial (IA) con proyectos como ACDC (Apple Chips in Data Center).

Este artículo está estrechamente relacionado con la ingeniería electrónica, ya que los avances en semiconductores son fundamentales en el diseño y desarrollo de dispositivos electrónicos. La carrera por desarrollar chips más avanzados, como los de 2 nm, implica innovaciones en la fabricación de componentes electrónicos a nivel nanométrico, lo cual requiere conocimientos especializados en áreas como la nanotecnología, la física de semiconductores y el diseño de circuitos integrados. Además, la incursión en el mercado de la IA y la fabricación de chips personalizados son áreas de creciente importancia para los ingenieros electrónicos, que deben estar al tanto de los últimos avances tecnológicos y contribuir al desarrollo de soluciones innovadoras en este campo.

# data[].attributes.attachment_link.readable_text
Apple quiere convertirse en la primera tecnológica en incluir chips de 2 nanómetros (nm) en sus smartphones. Para lograrlo está buscando una alianza estratégica con Taiwan Semiconductor Manufacturing Company Limited (TSMC), según un informe del diario Economic Daily News.

El reporte asegura que Jeff Williams, gerente de operaciones de la compañía de Cupertino, viajó a Taiwán para reunirse con Wei Zhejia, director ejecutivo de TSMC. Sugiere que han cerrado un nuevo acuerdo que garantiza que Apple será el primer cliente del proveedor oriental en recibir microprocesadores de 2nm.

Los nanómetros en un chip tienen la dimensión de los transistores, componentes que permiten la transferencia de energía entre las diferentes partes del circuito eléctrico. Cuanto menor es la variable, el procesador puede integrar más transistores y aumentar su potencia y consumo energético. Esto optimiza el rendimiento de los dispositivos y de sus apartados de carga.

El fabricante taiwanés ha informado que su procesador de 2 nanómetros comenzará a producirse en masa a partir de 2025. La tecnología de fabricación se conoce como N2 y será el primer nodo de producción de la compañía en emplear transistores GAAFET ( Gate-All-Around FET) que garantiza mayor rendimiento, escalabilidad y eficiencia energética.

El reporte de Economic Daily News sostiene que si la hoja de ruta de TSMC se cumple y el acuerdo de exclusividad con Apple se cierra, los microprocesadores de 2nm debutarían con el iPhone 17. El dispositivo de la compañía dirigida por Tim Cook aumentaría su rendimiento entre 10 y 15% respecto a los iPhone 15 Pro que trabajan con chips de 3nm. El gasto de energía se reduciría en 30%. Los analistas auguran que con un procesador más pequeño y más potente, el smartphone también llegaría con mejoras de diseño.

Apple quiere fabricar toda clase de chips

La empresa creadora del iPad está en búsqueda de alternativas que le permitan eliminar la dependencia que tiene con terceros en el desarrollo de chips. Su relación con TSMC se ha fortalecido desde el lanzamiento del M1, el primer semiconductor personalizado y diseñado bajo la plataforma Apple Silicon. La asociación comercial parece clave en la incursión de Apple en el mercado de la IA.

The Wall Street Journal informó a principios de este mes que la firma tecnológica está trabajando en un proyecto conocido como ACDC ( Apple Chips in Data Center). El objetivo es desarrollar y producir un microprocesador personalizado y enfocado en las fases de generación de contenido con IA. El informe precisa que proveedor taiwanés estaría a cargo de la producción del componente.

El productor de semiconductores presentó en abril su proceso de fabricación en nodo A16 de 1.6nm. La plataforma considera sumar transistores de nanolámina que integran en la parte trasera la solución de riel eléctrico conocida como 'Super Power Rail'. Ofrece una mejora de entre 8 y 10% en la velocidad de respuesta y un consumo de energía hasta 20% menor que su predecesor. TSM también anunció su tecnología System-on-Wafer (SoW) que permite integrar múltiples chips y componentes en una sola oblea de silicio. Esto aumenta de manera significativa la potencia de cálculo en espacios más pequeños. Ambas propuestas están diseñadas para soportar el funcionamiento de centros de datos con altas exigencias de rendimiento para productos de inteligencia artificial.

# data[].attributes.attachment_link.title
Apple quiere desarrollar el primer chip de 2 nanómetros y estrenarlo con el iPhone 17, según reporte

# data[].attributes.attachment_link.description
Apple será el primer cliente de TSMC en recibir microprocesadores de 2nm. El rendimiento del iPhone 17 podría mejorar entre 10 y 15% en comparación con el iPhone 15 Pro.

# data[].attributes.headline
Los semiconductores, el talón de Aquiles de la IA

# data[].attributes.subject
Los semiconductores, el talón de Aquiles de la IA

# data[].attributes.body
El artículo destaca la creciente importancia de los semiconductores en el contexto de la explosión de la Inteligencia Artificial (IA) y su impacto en los mercados accionarios mundiales. Se señala que la demanda de semiconductores, especialmente para el desarrollo de componentes eléctricos cruciales en la IA, está experimentando un fuerte aumento. Sin embargo, se destaca la preocupación por la oferta limitada de semiconductores, exacerbada por la proyección de un aumento del 13% en la demanda este año, particularmente impulsada por los chips de IA. A pesar de las iniciativas como la Ley de CHIPS en Estados Unidos, que busca impulsar la fabricación doméstica de semiconductores, se pronostica que la alta concentración del mercado continuará siendo un desafío en los próximos años, con Taiwán Semiconductor Company (TSMC) como un jugador estratégico clave que controla una gran parte del mercado.

Este artículo tiene una estrecha relación con la carrera de ingeniería electrónica, ya que los semiconductores son componentes esenciales en la fabricación de dispositivos electrónicos, incluidos los sistemas utilizados en la Inteligencia Artificial. La demanda creciente de semiconductores, impulsada por el auge de la IA, subraya la importancia de la ingeniería electrónica en la investigación, desarrollo y producción de estos componentes críticos. Además, las iniciativas gubernamentales para impulsar la fabricación local de semiconductores, como la mencionada Ley de CHIPS en Estados Unidos, resaltan la necesidad de profesionales en ingeniería electrónica para innovar en la producción y la oferta de semiconductores en un mercado cada vez más competitivo y estratégico.

Veronica Garcia Castro

# data[].attributes.headline
Ministerio y Universidad Purdue desarrollarán semiconductores RD

# data[].attributes.subject
Ministerio y Universidad Purdue desarrollarán semiconductores RD

# data[].attributes.body
En este articulo se habla del acuerdo entre el Ministerio de Industria, Comercio y Mipymes de la República Dominicana y la Universidad de Purdue de Estados Unidos marca un hito en el impulso de la industria de semiconductores en el país caribeño. Este convenio busca fortalecer el capital humano y promover el desarrollo nacional mediante la implementación de programas educativos, movilidad de profesores e investigadores, y proyectos de investigación conjunta centrados en el avance de la industria de semiconductores y otras áreas de alto valor añadido. Esto se alinea estrechamente con la carrera de ingeniería electrónica, ya que la formación de profesionales capacitados en STEM es esencial para el desarrollo económico y tecnológico, y la colaboración con una institución académica de renombre mundial como la Universidad de Purdue puede brindar oportunidades significativas para estudiantes e investigadores dominicanos en este campo.

La industria de semiconductores es fundamental en la ingeniería electrónica, ya que los semiconductores son la base de la mayoría de los dispositivos electrónicos modernos. Por lo tanto, el impulso de esta industria en la República Dominicana no solo puede contribuir al desarrollo económico del país, sino también ofrecer oportunidades de investigación, innovación y empleo en el campo de la ingeniería electrónica tanto a locales como extranjeros. Este acuerdo demuestra cómo la colaboración entre instituciones académicas y entidades gubernamentales puede promover el avance tecnológico y el crecimiento económico en un país, al tiempo que refuerza la importancia de la formación en ingeniería electrónica para satisfacer las demandas de una economía globalizada y digitalizada.

Veronica Garcia Castro

# data[].attributes.attachment_link.readable_text
Santo Domingo, 22 may.- El Ministerio de Industria, Comercio y Mipymes (MICM) firmó un acuerdo con la Universidad de Purdue, Estados Unidos, con el propósito de desarrollar la industria de semiconductores en la República Dominicana.

El acuerdo representa un "hito significativo" en los esfuerzos por fortalecer el capital humano y promover el desarrollo nacional, especialmente en la industria de semiconductores, afirmó el Ministerio en un comunicado.
LA ACADEMIA IMPLEMENTARÁ DIVERSAS ACTIVIDADES
El centro académico estadounidense, según el acuerdo, implementará diversas actividades de colaboración, incluyendo programas educativos en línea, movilidad de profesores, investigadores y estudiantes, y proyectos de investigación conjunta, todos ellos enfocados en impulsar el desarrollo de la industria de semiconductores en la República Dominicana y de otras áreas de alto valor añadido.

"Esperamos que esta asociación brinde oportunidades significativas para estudiantes, profesores e investigadores dominicanos", añadió el documento.
ENTIDADES CAPACITARAN PERSONAL
Mediante el acuerdo, Industria y Comercio y el Ministerio de Economía, realizarán la captación de talento humano en el país con sectores estratégicos como dispositivos médicos, productos farmacéuticos, aparatos eléctricos y electrónicos, semiconductores y las tecnologías de la información.

Este enfoque estratégico posicionará al país como un destino atractivo para inversiones en sectores clave, especialmente en la industria de semiconductores.

La presencia de talento capacitado en STEM, las siglas en inglés de ciencia, tecnología, ingeniería y matemáticas, es fundamental para el desarrollo económico y tecnológico, y este acuerdo podría ser un paso importante en esa dirección, agregó Industria y Comercio.

La información destacó que la Universidad de Purdue, ubicada en West Lafayette, Indiana, (EE.UU.), es una institución académica de renombre mundial, reconocida por su excelencia en educación, investigación e innovación, especialmente en las áreas de ingeniería, ciencia y tecnología.EFE

# data[].attributes.attachment_link.authors[].name
G Soluciones - Desarrollo web en santo domingo

# data[].attributes.attachment_link.title
Ministerio y Universidad Purdue desarrollarán semiconductores RD

# data[].attributes.attachment_link.description
Santo Domingo, 22 may.- El Ministerio de Industria, Comercio y Mipymes (MICM) firmó un acuerdo con la Universidad de Purdue, Estados Unidos, con el propósito de desarrollar la industria de semiconduct

# data[].attributes.headline
Electric double-layer transistors: a review of recent progress

# data[].attributes.subject
Electric double-layer transistors: a review of recent progress

# data[].attributes.body
En la investigación se habla sobre los transistores de capa doble eléctrica, que utilizan electrolitos para controlar la carga de los portadores en canales semiconductores. Se discuten materiales, técnicas de fabricación y aplicaciones en dispositivos de baja potencia y alta densidad. La importancia de esto es que los EDLT permiten una mayor miniaturización y eficiencia energética, fundamentales para dispositivos portátiles

Andres Mateo Chilito Avella :)

# data[].attributes.attachment_link.title
Electric double-layer transistors: a review of recent progress - Journal of Materials Science

# data[].attributes.attachment_link.description
With the miniaturization of electronic devices, it is essential to achieve higher carrier density and lower operation voltage in field-effect transistors (FETs). However, this is a great challenge in conventional FETs owing to the low capacitance and electric breakdown of gate dielectrics. Recently, electric double-layer technology with ultra-high charge-carrier accumulation at the semiconductor channel/electrolyte interface has been creatively introduced into transistors to overcome this problem. Some interesting electrical transport characteristics such as superconductivity, metal–insulator transition, and tunable thermoelectric behavior have been modulated both theoretically and experimentally in electric double-layer transistors (EDLTs) with various semiconductor channel layers and electrolyte materials. The present article is a review of the recent progress in the EDLTs and the impacts of EDLT technology on modulating the charge transportation of various electronics.

# data[].attributes.headline
A Comprehensive Review of Recent Progress on GaN High Electron Mobility Transistors: Devices, Fabrication and Reliability

# data[].attributes.subject
A Comprehensive Review of Recent Progress on GaN High Electron Mobility Transistors: Devices, Fabrication and Reliability

# data[].attributes.body
En el artículo podemos observar los múltiples avances en transistores de alta movilidad electrónica basados en GaN, abarcando desde la fabricación de dispositivos y las optimizaciones de procesos hasta las estructuras de dispositivos muy asombrosas. Se destacan los desafíos técnicos, como la fiabilidad y la integración con tecnologías CMOS de silicio, esto alineado con lo que hemos visto en clase. Además, los HEMTs basados en GaN ofrecen un rendimiento mucho mejor en términos de frecuencia y potencia comparado con los transistores de silicio, lo cual es muy útil en diversas aplicaciones

Andres Mateo Chilito Avella :)

# data[].attributes.attachment_link.readable_text
Department of Electrical and Electronic Engineering, Southern University of Science and Technology, Shenzhen 518055, Guangdong, China

Materials Characterization and Preparation Center, Southern University of Science and Technology, Shenzhen 518055, Guangdong, China

Shenzhen Key Laboratory of the Third Generation Semi-conductor, Shenzhen 518055, Guangdong, China

GaN Device Engineering Technology Research Center of Guangdong, Shenzhen 518055, Guangdong, China

Authors to whom correspondence should be addressed.

1. Introduction

Nitride-based wide band-gap semiconductors (WBS), such as GaN and related alloys, have been intriguing to high power and high frequency researches and applications over the past two decades, as reviewed in the literatures [ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10]. They are promising because of their intrinsic superior material properties, especially with their outstanding electrical performance exhibited in the GaN-based high-electron mobility transistors (HEMTs), also known as the heterojunction field-effect transistor (HFET). GaN-based HEMTs on silicon substrate are particularly appealing to the IC industry due to its compatibility with the industry-matured Si-CMOS IC technologies. Tremendous research and development work has been conducted and reported in the recent years with significant progresses on GaN-on-Si HEMTs covering the full scope of a new IC-chain, including the industrial acceptable-low defect quality of GaN-on-Si epitaxial materials, the optimized GaN-based HEMT devices and integration [ 11, 12, 13, 14, 15, 16, 17], the significantly enhanced reliability [ 18, 19, 20, 21, 22, 23, 24], the comprehensive circuit and device modeling [ 25, 26, 27] and the product designs [ 19, 28, 29, 30, 31, 32, 33, 34].

The GaN-based HEMTs possess better performance than the silicon counterparts, such as they can be operated at higher frequency, higher power and higher temperature conditions. These advantages are benefited from III-nitrides' high electron saturation velocity, high breakdown electrical field, high electron mobility and high carrier density of the two-dimensional electron gas (2DEG) formed at the heterointerface between AlGaN and GaN layers in the GaN HEMTs.

GaN power transistors have been in volume production since 2010. AlGaN/GaN HEMT, however, is inherently normally-ON (depletion-mode, D-mode) as it was first reported in 1993 [ 35]. Thus their primary applications having been initially focused on the low-voltage and high-frequency applications. For the power switching applications, on the other hand, normally-OFF (enhancement-mode, E-mode) transistors are required. It is not only for the concern of safety but also necessary to reduce the current leakages thus minimize the power loss, simplify the driving circuit and improve the device stability. Ever since the initial demonstration of the enhancement-mode AlGaN/GaN HEMT in 1996 [ 36] and furthermore in 2000 [ 37], several approaches have been used to make normally-OFF GaN-based HEMTs as reviewed previously [ 38] and more recently [ 8, 39]. Besides the hybrid approach with GaN HV-HEMT and Si LV-MOSFET in a cascade configuration, AlGaN/GaN-on-Si HEMTs with direct GaN gate control [ 40, 41] have attracted much attention commercially in the recent years due to its size thus cost. GaN-on-Si is acknowledged as a promising device platform for further exploration of commercial high-power modules with higher power density [ 4, 9, 33, 34]. Moreover, owing to the availability of both depletion-mode and enhancement-mode of GaN HEMTs, they have invoked research interests and efforts in the IC industry for complementary logic applications [ 9, 31].

This paper reviews the recent progress in the GaN-on-Si normally-OFF AlGaN/GaN HEMTs based on recent literature. The following aspects will be covered: devices in Section 2, device fabrication in Section 3 and some promising structures from simulation studies in Section 4.

2. AlGaN/GaN HEMT Device

For conventional semiconductor materials, the free charges come from the impurity ionization. In an AlGaN/GaN heterojunction, the polarization effects give rise to a high density (>1 × 10 ¹³ cm ⁻²) of electron gas at the interface between AlGaN and GaN, even without intentional doping. The AlGaN/GaN HEMTs can provide not only high electrical conductivity with low on-state resistance but also low input and output capacitance, thus inherently promising for high voltage and high frequency applications.

A conventional Schottky gate D-mode GaN HEMT device structure is schematically shown in Figure 1a. The source and drain metal stacks facilitate the Ohmic contacts. The gate metal stack provides a Schottky contact. As a voltage bias of V DS is applied between the drain and source, a lateral electrical field is built and the 2DEG under the gate flows along the channel of AlGaN/GaN heterojunction as HEMT's current, I DS. If the gate voltage is below the threshold voltage of HEMT while the drain is biased high, the device runs into the block region.

When the AlGaN/GaN HEMT in Figure 1a is inserted with a p-type GaN layer between the gate electrode and the AlGaN barrier layer, it forms a so-called p-GaN E-mode HEMT as shown in Figure 1b. With sufficiently high p-type doping (e.g., Mg) and an adequately thick p-GaN layer, the 2DEG below the gate would be depleted, which lead to a positive threshold voltage for the normally-OFF operation. Meanwhile, the low on-state resistance and high driving capability can be preserved with the 2DEG in the region between the gate edge and the drain. More advanced research work has been done in order to solve dynamic on-state resistance issues in GaN HEMTs. One of these successful examples has the current collapse suppressed up to 850 V [ 42]. There are also several varieties of p-GaN HEMTs as thoroughly reviewed in References [ 8, 39], such as the gate injection transistor (GIT) [ 42].

Several advanced types of AlGaN/GaN FET devices have been explored recently. Among of them, the GaN MOS or MIS (metal-insulator-semiconductor) HEMTs has drawn most of the attention [ 9, 14, 28, 43], so do the MISHEMTs with high-K gate dielectric [ 17, 31, 44]. Other new devices with a regrowth of AlGaN layer [ 41], or a regrowth of GaN drift channel layer [ 45] have also been reported. The MIS HEMT has the advantages over the Schottky gate GaN HEMT in terms of gate leakage and gate swing [ 46]. The gate dielectrics reliability, however, is one of the most important aspects to be well investigated and understood before it can be commercialized.

The performance of some recently published p-GaN HEMT devices [ 19, 42, 47, 48] is compared and shown in Figure 2. It depicts the p-GaN HEMTs with excellent specific on-resistance R on,sp as low as a few mΩ∙cm ² while with the breakdown voltages larger than the theoretical limit of silicon.

Figure 3 demonstrates the preliminary DC characteristics of the fabricated p-GaN E-mode AlGaN/GaN HEMT. The device gate width is about 500 μm. The metal stack for the source and drain Ohmic contacts was formed with Ti/TiN/Al/TiN and was annealed at 650 °C for 30 s. And the metal stack for Schottky contact for the p-GaN gate was formed with Ti/Al. The detailed process information will be discussed in a subsequent publication. The measurements were carried out with keithley 4200-SC. The transfer characteristics (I DS-V G) of the device is shown in Figure 3a and the output characteristics (I DS-V DS) of the device is illustrated in Figure 3b. The threshold voltage (V th) of the fabricated device is about 1.5 V and the gate voltage swing is up to 10 V.

One of the challenges of making reliable p-GaN gate enhancement-mode HEMTs is to obtain controllable V th with a reasonable variation across the wafer. It is found that V th is sensitive to the p-GaN gate profiles, p-GaN layer residues, AlGaN layer thickness around the gate edges and also surface morphology of the AlGaN layer after the p-GaN etching. The threshold voltage instability can be explained by the charge control model due to the charge-transferring effect [ 49, 50]. The enhancement of threshold voltage in E-mode AlGaN/GaN devices is mainly due to the space charge alteration under the gate, while defects can alter the charges via trapping and de-trapping processes during device operations. The fixed defects in the GaN and AlGaN layers can act like traps offering electron transferring paths between the barrier layer and the substrate, which can generate potential shift and energy band bowing, thus V th drift. Therefore, the reduction of defects is mandatory for reducing the charge variations so as to control the threshold voltage instability and reliability. Achieving low defects in III-nitrides layers, however, requires careful process engineering and optimizations.

Regarding to the device reliability of GaN-on-Si HEMTs [ 51], it has been recently figured out that the epitaxial quality of materials is related to a key industrial reliability item: the high temperature reverse bias (HTRB) stress-induced on-state drain current degradation [ 18]. It was confirmed [ 18] that the optimization of epitaxial layers could significantly improve the device reliability of AlGaN/GaN HEMTs.

We have also studied the dielectric failure based on the time dependent dielectric breakdown (TDDB) measurement at different temperatures with statistical Weibull analysis [ 24]. The lifetime of the devices with 35-nm-thick LPCVD SiN x gate dielectric was predicted to have a 10-year time-to-breakdown. This work also demonstrated the impacts of gate dielectric area and multi-fingers on the SiN x TDDB characteristics.

3. AlGaN/GaN HEMT Device Fabrication

Device processing technologies play important roles to achieve the full-potential and remarkable features of AlGaN/GaN HEMTs. The process modules for the GaN HEMT device fabrication include device isolation, p-GaN gate formation, contacts for source and drain, contact for gate, surface passivation and so forth. In this section, we will focus on some of the key process technologies for the fabrication of p-GaN E-mode AlGaN/GaN HEMTs, discuss some of the challenges and review recent progresses.

3.1. Device Isolation

Device isolation is the fundamental process to separate the electrical connection of adjacent devices, so as to minimize the impact of current leakage from their neighbors. Mesa dry etching and ion implantation are two of the commonly used and effective isolation approaches as shown in Figure 4.

3.1.1. Mesa Etching

The mesa etching step is to form an isolated area for each device and the material is removed physically around the devices by this process, as shown in Figure 4a. The etching depth is crucial for the isolation results or device leakage current. Under-etch of the mesa could result in an incomplete isolation, thus the devices performance would be impacted. The conventional wet etch techniques are not suitable for GaN device fabrication. The large bond energies and wide band-gaps make them highly resistant to acid and alkaline solutions at room temperature. Moreover, the wet etching of GaN shows isotropic profile and a slower etching rate than the dry etching techniques. Therefore, most of III-nitrides etching processes are conducted by dry etching [ 52].

Dry etching can be carried out by reactive ion etch (RIE), electron cyclotron resonance (ECR), inductively coupled plasma (ICP), electron cyclotron resonance (ECR), magnetron reactive ion etching (MIE) and so forth. [ 53]. RIE is one of the common methods for III-nitrides dry etching but it has slow etching rate, low degree of anisotropy and large surface damages due to the low plasma density and high operating pressure inherent in this technique [ 54]. Whereas ICP is expected to produce the etching results with low damages, high etching rates and high uniformity. Thus ICP etching has become the dominant dry etching technique for III-nitrides.

The dry etching rate can reach to the level of micron per minute handily [ 55, 56]. However, many factors need to be considered to evaluate the dry etching quality of GaN and AlGaN, such as the surface morphology, sidewall profile, etching anisotropy, material selectivity, material damage, etching uniformity and so forth. These etching features can be affected by the etching conditions, including reactive chemistries and their fluxes, ICP antenna RF power, bias RF power, chamber pressure, chamber temperature, chamber configuration, etching technique and so forth.

The basic chemistries employed in the III-nitrides dry etching are chlorine based, such as Cl ₂ and BCl ₃ [ 57]. Moreover, Ar [ 52], N [ 54], H [ 58] and F [ 59] based chemistries can also be added to achieve better etching rate, selectivity and surface morphology [ 60]. Study [ 57] showed that the etching rate was found to increase with the ICP antenna RF power up to a certain level (e.g., 600 W). But further increased in antenna RF power could decrease the etching rate. It is noticed [ 54] that a high antenna RF power would cause the decrement of the DC bias voltage and thus resulting in a reduction of the ion-bombardment physical effect introduced by dry etching. High energy ion-bombardment would lead to surface roughness, material surface damages and low etching selectivity. Wakejima et al. [ 61] reported that the reasonably low bias RF power can be used to get high selectivity and low surface damage. Moreover, chamber pressure also has an impact on the etching rate. Increase chamber pressure (within the range of less than 10 mTorr) can help raise the etching rate. But further increase chamber pressure would not keep increasing the etching rate effectively. The mean free path of reacting molecules is short and the plasma density is low at high pressure. Re-deposition and polymer formation on the surfaces would also be favored at high pressure, which is undesirable [ 57].

3.1.2. Ion Implantation

Ion implantation is the other isolation process which is promising to product high performance GaN based HEMTs devices [ 15]. Ion implantation is an adding process, as shown in Figure 4b. The ion species can be used to isolate devices including H, He, N, P, Ar, O and so forth [ 62, 63, 64, 65, 66, 67]. In the implantation process, atoms are added into the nitrides by means of energetic ion beam injection. Ion implantation has a better ability to control both of the dopant concentration and depth. The concentration can be adjusted by the ion beam current and the implantation duration, while the depth can be controlled by the ion energy.

The ion implantation is a room-temperature process; thus photoresist can be used as the mask. The ion species that implanted can be exactly selected by the mass analyzer, thus the contamination risk can be reduced. Moreover, the ion implantation is an anisotropic process, the side boundary of the implanted ions in the semiconductors can be straight. Thus the isolated area can be precisely defined. However, for the purpose of minimizing the channeling effect, the wafers are always placed with a tilted angle of about 7°.

Comparing to the mesa etching process, the ion implantation creates the isolation boundary under the surface, which can protect the device sidewalls. Therefore, better device electrical performance and reliability are expected.

3.2. P-GaN Gate Formation

To achieve the E-mode GaN based HEMTs, the structure of p-GaN HEMTs has been widely used [ 51]. As shown in Figure 5, the basic structure of the p-GaN HEMT consists of the p-GaN cap layer, AlGaN barrier layer, GaN buffer layer, Si substrate and so forth. The energy bands of AlGaN are lifted up by the p-GaN cap layer, leading to the depletion of the 2DEG underneath. The p-GaN should be removed except for the gate area. The dry etching is widely used for this step. One of the key factors to achieve high performance device and high yield is the selectivity etching of GaN over AlGaN. The selectivity of Cl ₂/BCl ₃ plasma between GaN and AlGaN is unable to meet the requirement. Therefore, two approaches have been recommended to achieve this process of selective dry etching. One is the fluorine based chemistries etching technique and the other is oxygen based chemistries etching technique.

The etching selectivity of compound semiconductor films containing Al can be optimized in Cl-based plasmas by adding F-containing gases. For example, the BCl ₃/SF ₆ selective dry etching on AlGaN/GaN, the decrease in AlGaN etching rate is due to the formation of non-volatile AlF ₃ residues on AlGaN surface. This non-volatility of AlF ₃ reduces the etching efficiency of chlorine, achieving selective etching of GaN over AlGaN.

The other option is to use the O ₂ and chlorine based gases. Shawn et al. [ 68] demonstrated a cyclical two-step etching technique using separate O ₂ and BCl ₃ plasmas. The low power oxygen plasma creates an oxidized layer on the surface of AlGaN/GaN and then the low-power BCl ₃ plasma is used to remove the surface oxide. The etching rate per cycle is about 0.7-2.5 nm, depending on the process parameters. Wong et al. [ 69] investigated highly selective dry etching with O ₂ and chlorine gases. Their study showed that the O ₂ flow has evident impacts on the etching rate and selectivity of AlGaN/GaN structure. Increasing O ₂ flow (0-5 sccm) resulted in decrease etching rates for both GaN and AlGaN. The selectivity was increased at the O ₂ flow range of 0-2 sccm and then descended when O ₂ flow arrived at 3 sccm. Moreover, they reported that the surface roughness was improved with a higher O ₂ flow.

To achieve high etching selectivity, some new structures have been developed. Chiu et al. [ 70] reported that they added an AlN etching stop layer between p-GaN and AlGaN, that is, the p-GaN/AlN/AlGaN/GaN structure, to improve the p-GaN etching selectivity. With the BCl ₃ and CF ₄ gas mixture, the etching rate can be slowed down remarkably on AlN layer due to the non-volatility of AlF ₃. Then they obtained a better uniformity of V th compared with the conventional structure. The standard deviation of V th from the devices with AlN stop layer was about 0.06 V, whereas the data from the traditional ones was 0.2 V. Moreover, they further employed N ₂O as the oxidant [ 71] with the same AlN stop layer and achieved further improved uniformity. The p-GaN was oxidized to Ga ₂O ₃ by N ₂O plasma and then the Ga ₂O ₃ was removed using HCl solution in one cycle. After p-GaN was fully removed, the AlN etching stop layer was exposed and oxidized to Al ₂O ₃ by N ₂O plasma. Since the etching rate of this Al ₂O ₃ in HCl solution was extremely low, the selective etching of AlGaN/GaN was achieved. They claimed that the uniformity of device on-state resistance (R on) and the surface leakage current were improved both by this technique.

For the purpose of controlling the uniformity of threshold voltage, reducing the device leakage current and improving device reliability performance, more efforts have to be made to achieve smooth surface morphology, low material damages, high etching selectivity and outstanding etching uniformity.

3.3. Ohmic Contacts for Source and Drain

The Ohmic contacts provide the access points for the device to connect with external circuitry. Their resistance should be very low with respect to that of the channel drift region to reduce the device specific on-resistance. It is rather challenging to make good Ohmic contacts on GaN based materials, owing to the wide band-gap which naturally facilitates Schottky contacts. For the high performance p-GaN HEMT, the source/drain Ohmic contact resistance (R c) should be minimized. Thus the work function metal layers, the thickness of metal layers, annealing temperature, semiconductor doping level, recess depth of AlGaN layer and so forth. are all important factors to be optimized. The structure of source and drain contacts are displayed in Figure 6.

Single metal layer is not commonly used such as Ti or Al, due to their chemical activity with oxidant, especially for high power devices which often work at high temperatures. Therefore, different metal stacks with multiple layers have been proposed and explored. These metal stacks can be categorized into two groups, Au-based metal stacks and Au-free metal stacks. Au-based metal stacks have been studied for many years and become mature gradually. The most used stacks include Ti/x/x/Au structures [ 72], where x represents metals such as Al, Ni, Ti, Mo and so forth. On the other hand, the Au-free metal stacks are highly recommended recently for CMOS compatible process. The process compatibility with current Si wafer line is a fundamental factor of whether the GaN based devices can be fabricated in foundries, or even in the reused 6 or 8 inch Si wafer process lines. This means metals such as Au and Cu need to be excluded from the front-end-of-line.

Ti/Al/Ni/Au is widely used for source and drain Ohmic contacts. Studies [ 73, 74] showed that the formation of Ohmic contacts for Ti based metal stacks is due to the reaction between Ti and GaN. TiN is formed at the interface by which N vacancies are created as donors to increase the carrier concentration resulting in a thinner barrier for electron tunneling [ 73]. In the Ti/Al/Ni/Au metal stack, thickness of each metal layer needs to be optimized to achieve low contact resistance and smooth surface. Ti/Al thickness ratio in the metal stack is one of the key factors for the formation of low contact resistance [ 75]. Research showed that for a given Ni/Au thickness ratio, the lowest contact resistance is obtained at Ti/Al ratio of 1/6 when annealing at 900 °C in N ₂ ambient [ 76]. Moreover, the total thickness of Ti/Al also strongly influences the final contact resistance. Generally, the contact resistance below 0.6 Ω∙mm can be commonly obtained in the Ti/x/x/Au metallization.

Au-free processes have been reported for many kinds of metal stacks. Beyond the consideration of compatibility with the Si-wafer-process-line, the research of Piazza et al. [ 77] demonstrated that long term thermal stress of Ti/Al/Ni/Au metal stack could led to a dramatic degradation of the structure. This could be a barrier for the high power applications of the GaN based devices. Lee et al. [ 11] reported Ti/Al/W metal stack for Ohmic contacts. The contact resistance was lower than 0.5 Ω∙mm with the annealing temperature of 870 °C. The surface morphology of the Ti/Al/W metal stack was much smoother than that of the Ti/Al/Ni/Au metal stack.

Annealing temperature of metal stack is important for the formation of Ohmic contacts. Most Au-based and Au-free metal structures are annealed around 800 °C [ 72, 78], while some work reported low temperature (lower than 700 °C) annealing to achieve Ohmic contacts [ 79, 80].

Liu et al. [ 81] reported the Hf/Al/Ta metal stack on InAlN/GaN with the annealing temperature of 600 °C. The results from TEM and SIMS measurements revealed contacts with smooth metal-semiconductor interface and showed the formation of Hf-N and Hf-Al alloys near the interface. They achieved a specific contact resistance (ρ c) of 6.7 ± 0.58 × 10 −6 Ω∙cm ² at 600 °C annealing temperature. Lin et al. [ 82] presented a low Ohmic contacts resistance formed by sidewall contacts with Ohmic recess. They used a Ta/Al/Ta metal stack with the annealing temperature of lower than 600 °C. For the recess depth of 10 nm, they achieved contact resistance of lower than 0.25 Ω∙mm. Ti/Al/TiN metal stack is also used for Ohmic contacts. Firrincieli et al. [ 80] employed the Ti/Al/TiN metal stack annealing at 550 °C in N ₂ ambient and achieved a contact resistance of 0.62 Ω∙mm. This metal stack was also shown to pass a high current of 0.6 A/mm when 10 V bias was applied.

Recently, Yoshida and Egawa [ 83] reported Ti/Al/W Ohmic contacts on AlGaN/GaN. The contact resistance was about 0.358 Ω∙mm with a low annealing temperature of 500 °C. They found that thinner Ti layer can lead to a lower annealing temperature, because Al needs to diffuse through the Ti layer in order to make Ohmic contact with AlGaN. Pozzovivo et al. [ 84] studied the effects of a special SiCl ₄ plasma treatment prior to the Ohmic metallization. They achieved a sufficiently low contact resistance of 0.7 Ω∙mm at a reduced anneal temperature of 600 °C. The contact surfaces of AlGaN were directly treated by the SiCl ₄ plasma for 15 s in RIE with self-induced bias of about 300 V. They suggested that the SiCl ₄ plasma treatment of AlGaN surface would help to enhance the generation of N vacancies, which may be responsible for the high carrier concentration at the AlGaN surface to form a low contact resistance. The work from Graff et al. [ 75] exhibited consistent results of low contact resistance with the pre-treatment of SiCl ₄.

The low annealing temperatures and the Au-free metal stacks would be beneficial to the device electrical and reliability performance [ 83] and are also compatible with foundry CMOS processes which is plausible for transferring to large scale production.

3.4. Contact for Gate

For the p-GaN E-mode HEMTs, the Schottky contacts on gate are generally adopted because it is expected to have lower gate leakage current and higher thermal stability. Figure 7 illustrates the gate structure of a typical p-GaN HEMT. The metal-semiconductor Schottky barrier height is depending on the difference between the work function of metal and the electron affinity of semiconductor. Metal with lower work function should give a higher barrier height for p-GaN contact. The Ti/Al [ 85], Ni/Au [ 86], W [ 87] and so forth. are used for gate metals. Greco et al. [ 85] studied the impacts of the thermal budget on the Schottky gate metals of Ti/Al. They found annealed with 800 °C of Ti/Al stack resulted in a higher gate leakage current than that of annealed at lower temperature. The decrease of the Schottky barrier height from 2.08 to 1.60 eV with annealing temperature increased to 800 °C was attribute to the structural modification occurring at the interface, which explained the increase of the leakage current.

Ťapajna et al. [ 88] studied the Schottky gate reliability under forward bias stress of a p-GaN HEMT. They concluded that the generation-recombination centers were created during stress due to the defect percolation process. This stress-induced generation of defects formed the leakage path across the structure once sufficient defects are generated. Wu et al. [ 89] revealed that the gate breakdown phenomenon could be explained by the avalanche multiplication in the space charge region of the Schottky metal/p-GaN junction. Tallarico et al. [ 90] concluded that the time to failure is a function of the initial Schottky gate leakage and the breakdown mechanism is ascribed to the percolation path in the p-GaN layer. Stockman et al. [ 91] studied the Schottky gate leakage current under the reverse gate bias. Two efficient methods to suppress the perimeter-dependent leakage current were found. One is by improving Schottky/p-GaN interface quality to reduce the supply of carriers from the gate metal, the other is by making proper passivation of the p-GaN sidewalls to reduce the interface states and surface roughness.

Yu et al. [ 92] also concluded that the gate leakage current is likely due to a highly doped and/or highly defective surface layer, resulting in carrier transport by tunneling across the Schottky barrier. Lu et al. [ 86] demonstrated the results of employing surface treatment and post-gate annealing to improve the Schottky gate leakage. The surface treatment reduced the lateral surface leakage by removal of the surface traps. The vertical gate tunneling current, on the other hand, was lowered through improved Schottky contact quality after thermal annealing. The off-state leakage current was reduced by about 7 orders after the implementation of the two-step treatment.

Besides the approaches of using the Schottky contacts, an Ohmic gate contact is suggested by Panasonic [ 42]. They reported that the hole-injection from the p-GaN gate into the GaN channel could have a positive impact on the p-GaN gate module.

As we can see, the gate metallization for p-GaN E-mode HEMTs has profound impacts on the device performance. For Schottky gate contacts, low gate leakage current and high thermal stability are required.

3.5. Surface Passivation

Although significant progress has been achieved to improve the performance of GaN devices, noticeable gaps still remain between demonstrated device performance in the real market applications and the theoretical expectations. The existence of large amount of surface states in AlGaN and GaN have been found to be the root cause of device current collapse and some reliability issues, which is one of the main challenges in fabricating high performance AlGaN/GaN HEMTs [ 93, 94, 95, 96, 97]. These surface states may come from dangling bonds of the surface atoms, defects at the surface as grown, plasma damages during the processes, the foreign contaminations and so forth. And they behave like carrier traps thus can seriously deteriorate the device performance. Furthermore, the charged surface states can act as a virtual gate and lead to the depletion of channel electrons, thus decreasing the channel 2DEG density [ 98]. The trapped charges at the surface can also contribute to the remote Coulomb scattering to the channel electrons. Therefore, surface passivation should be carefully optimized to prevent negative effects on device performance such as current collapse, frequency dispersion, large dynamic on-resistance and so forth.

The basic structure of surface passive layer is illustrated in the Figure 6. Many different insulation materials have been explored as the surface passivation layer for AlGaN/GaN HEMTs, including SiO ₂ [ 93, 99], Si ₃N ₄ [ 100], ZrO ₂ [ 94, 101], HfO ₂ [ 95, 96], Ga ₂O ₃ [ 43, 102], AlN [ 103, 104, 105, 106], Sc ₂O ₃ [ 107], TiO ₂ [ 108], ZnO ₂ [ 109], NiO [ 110], Ta ₂O5 [ 111], Al ₂O ₃ [ 112, 113, 114], AlON [ 43] and so forth. In addition to the surface passivation, dielectric-free passivation technologies have also been proposed and demonstrated, for example, oxygen plasma oxidization [ 115, 116], ozone oxidization [ 117], chemical oxidization [ 118], SiH ₄ treatment [ 119] and so forth. AlN is found to be a good surface passivation layer which can create a sharp interface and suppress GaN surface oxidation effectively [ 120]. Recently, Panasonic developed a passivation technology with AlON layer [ 43]. The AlON layer was deposited by atomic layer deposition (ALD) possessing a better performance with less process damage, less extra fixed charges and less electron traps in comparison with Al ₂O ₃ layer. Moreover, O ₂ annealing after the AlON deposition could further reduce the Al/Ga dangling bonds at the surface.

It is known that GaN can be oxidized in the air forming a layer of native gallium sub-oxide (GaO x) on the surface. Defect states associated with the GaO x further exacerbate gate leakage current and lead to drain-current collapse at high frequency [ 121, 122, 123]. Dong et al. [ 124] have proposed a method to reduce the surface states by changing the GaO x morphology via an elevated-temperature. The ordering of native GaO x layer can be improved towards the structure of bulk Ga ₂O ₃, therefore surface states can be reduced. Bae et al. [ 125] used a low-temperature treatment to enhance the quality of GaO x formed at the SiO ₂/GaN interface and thus reduce the interface defect density. Therrien et al. [ 126] demonstrated a microscopic mechanism that could reduce the defect density at the high-K/GaN interface through the formation of a high-quality Ga ₂O ₃ layer during remote-plasma-assisted oxidation. It should be noted that the high dielectric constant of the surface passivation layer can also increase the parasitic capacitance between the gate and source (C pgs)/drain (C pgd) metals and thus decrease the device's speed [ 127]. In summary, surface passivation with dielectric layers should be carefully selected to improve device performance, eliminate the current collapse and reduce the dynamic on-resistance.

3.6. Field Plates

As we have mentioned above, GaN based HEMTs suffer the effect of current collapse [ 128], which can temporary increase the dynamic on-resistance due to the charge trapping effects. One reason is that the strong electric field at the gate edge on the drain side could enhance the charge trapping in the states at the interface between passivation and III-nitrides. Moreover, the hot-electron injection effect is considered to be the other reason for the current collapse [ 129]. Surface passivation [ 130] and field-plate [ 131] are two effective solutions for this issue.

The employment of a field plate on dielectric layer of the AlGaN/GaN HEMT has brought some of the most significant and exciting improvements on current collapse [ 129]. The function of the field plate is to redistribute the electric field profile and decrease the electric field peak value, hence reducing trapping effect and increasing breakdown voltage, as presented in Figure 7. Recently, Wong et al. [ 132] demonstrated a novel asymmetric field plate structure. The electric field was appropriately distributed by the slanted field plate. They obtained a uniform electric field distribution with the slant field plate, achieved a reduced dynamic on-resistance of 2.3 Ω∙mm at the drain voltage of 50 V with a high breakdown voltage up to 138 V. Ma et al. [ 133] studied the effects of surface treatment and field plate structures on the current collapse of the AlGaN/GaN HEMTs. Their results showed that the gate field plate predominantly reduced the emission time constant of the trapped electron and O ₂ plasma treatment decreased the density of traps. And they confirmed that the current collapse can be mitigated by the combination of these two methods.

4. AlGaN/GaN Device Simulation

The technology-computer-aided-design (TCAD) simulations are often applied to study the AlGaN/GaN HEMT. The focus is mainly on the E-mode mechanism as well as the methods of increasing the threshold voltage of the HEMTs [ 134, 135]. And the simulations have also been used to study the gate leakage current [ 136, 137], the device reliability [ 138], the short channel effects [ 139], current collapse [ 140] and so forth. For the simulation of the AlGaN/GaN HEMTs, the most important work is to solve the 2DEG concentration which is generated by spontaneous polarization (P sp) and piezoelectric polarization (P pe) [ 141], as shown in Figure 8. The two polarizations are influenced by many factors, such as the materials of substrate and epitaxial layers, crystallographic plane orientation of III-nitrides, AlN composition of AlGaN layer, thickness of AlGaN layer, relaxation of AlGaN layer, doping concentration in AlGaN layer, thickness of GaN cap layer, fabrication process and so forth [ 142, 143, 144, 145, 146, 147, 148, 149]. For the p-GaN HEMTs simulation, there are many valuable studies have been reported [ 39, 142, 143, 144, 145, 150]. For example, Fujii et al. [ 151] presented the control of threshold voltage by the variation AlGaN barrier layer thickness and AlN molar fraction. Efthymiou et al. [ 152] investigated effects of the p-GaN doping and gate metal work function on the threshold voltage of devices. Bakeroot et al. [ 153] developed an analytical model for calculation of the threshold voltage for p-GaN HEMTs, they studied the contributions of p-type doping profile, AlN molar fraction of AlGaN layer and AlGaN layer thickness to the threshold voltage.

Moreover, in addition to the structures of p-GaN gate, recess gate and F-treatment, some novel E-mode HEMTs have been also proposed and studied through simulations. Huang et al. [ 154] simulated an E-mode HEMT with a floating gate in the gate dielectric. The results showed that combining with the gate recess, the V th of the devices could be larger than 3 V with a low sheet density of ~10 ¹² cm −2. Wang et al. [ 155, 156] simulated an E-mode HEMT with spilt floating gate. It is shown that such kind of device can improve the charge retention time comparing with the single floating gate HEMTs [ 157]. Duan et al. [ 158] simulated an E-mode HEMT with Groove-type channel and the normally-off function was based on the anisotropic polarization of GaN.

5. Summary

In this review, we have evaluated the recent progress of GaN based E-mode HEMTs. First, the typical device performance has been presented. And then we focused on some of the key technologies for fabricating p-GaN E-mode AlGaN/GaN HEMTs, including device isolation, p-GaN gate formation, Ohmic contacts for source and drain, contact for gate, surface passivation and field plate. For the material and device simulations, we reviewed some of the promising structures for achieving high performance E-mode devices. In summary, this paper provides the recent developments and existing challenges of p-GaN E-mode AlGaN/GaN HEMTs, we hope this could be useful for the study of E-mode AlGaN/GaN HEMTs.

Author Contributions

All the authors contributed equally. All the authors read and approved final manuscript.

Funding

This work was funded by Research of Low Cost Fabrication of GaN Power Devices and System Integration (grant number: JCYJ20160226192639004), Research of AlGaN HEMT MEMS Sensor for Work in Extreme Environment (grant number: JCYJ20170412153356899) and Research of the Reliability Mechanism and Circuit Simulation of GaN HEMT (grant number: 2017A050506002).

Conflicts of Interest

The authors declare no conflict of interest.

References

1. Treu, M.; Vecino, E.; Pippan, M.; Haberlen, O.; Curatola, G.; Deboy, G.; Kutschak, M.; Kirchner, U. The role of silicon, silicon carbide and gallium nitride in power electronics. In Proceedings of the 2012 International Electron Devices Meeting, San Francisco, CA, USA, 10-13 December 2012; pp. 7.1.1-7.1.4. [Google Scholar]

2. Ueda, D. Renovation of power devices by GaN-based materials. In Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 7-9 December 2015; pp. 16.4.1-16.4.4. [Google Scholar]

3. Piedra, D.; Lu, B.; Sun, M.; Zhang, Y.; Matioli, E.; Gao, F.; Chung, J.W.; Saadat, O.; Xia, L.; Azize, M.; et al. Advanced power electronic devices based on Gallium Nitride (GaN). In Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 7-9 December 2015; pp. 16.6.1-16.6.4. [Google Scholar]

4. Deboy, G.; Treu, M.; Haeberlen, O.; Neumayr, D. Si, SiC and GaN power devices: An unbiased view on key performance indicators. In Proceedings of the 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3-7 December 2016; pp. 20.2.1-20.2.4. [Google Scholar]

5. Yu, H.; Duan, T. Gallium Nitride Power Devices; Pan Stanford: Singapore, 2017. [Google Scholar]

6. Lidow, A.; Strydom, J.; de Rooij, M.; Reusch, D. GaN Transistors for Efficient Power Conversion; Willey: New York, NY, USA, 2015. [Google Scholar]

7. Meneghini, M.; Gaudenzio, M.; Zanoni, E. Power GaN Devices-Materials, Applications and Reliability; Springer: New York, NY, USA, 2017. [Google Scholar]

8. Tsai, C.-L.; Wang, Y.-H.; Kwan, M.H.; Chen, P.C.; Yao, F.W.; Liu, S.C.; Yu, J.L.; Yeh, C.L.; Su, R.Y.; Wang, W.; et al. Smart GaN platform: Performance & challenges. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2-6 December 2017; pp. 33.1.1-33.1.4. [Google Scholar]

9. Meneghesso, G.; Meneghini, M.; Zanoni, E. Gallium Nitride-Enabled High Frequency and High Efficiency Power Conversion; Springer: New York, NY, USA, 2018. [Google Scholar]

10. Stoffels, S.; Zhao, M.; Venegas, R.; Kandaswamy, P.; You, S.; Novak, T.; Saripalli, Y.; Van Hove, M.; Decoutere, S. The physical mechanism of dispersion caused by AlGaN/GaN buffers on Si and optimization for low dispersion. In Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 7-9 December 2015; pp. 35.4.1-35.4.4. [Google Scholar]

11. Marcon, D.; Saripalli, Y.N.; Decoutere, S. 200mm GaN-on-Si epitaxy and e-mode device technology. In Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 7-9 December 2015; pp. 16.2.1-16.2.4. [Google Scholar]

12. Zhang, Z.; Li, B.; Tang, X.; Qian, Q.; Hua, M.; Huang, B.; Chen, K.J. Nitridation of GaN surface for power device application: A first-principles study. In Proceedings of the 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3-7 December 2016; pp. 36.2.1-36.2.4. [Google Scholar]

13. Wang, J.; Cao, L.; Xie, J.; Beam, E.; McCarthy, R.; Youtsey, C.; Fay, P. High voltage vertical p-n diodes with ion-implanted edge termination and sputtered SiNx passivation on GaN substrates. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2-6 December 2017; pp. 9.6.1-9.6.4. [Google Scholar]

14. Wong, K.-Y.; Lin, Y.S.; Hsiung, C.W.; Lansbergen, G.P.; Lin, M.C.; Yao, F.W.; Yu, C.J.; Chen, P.C.; Su, R.Y.; Yu, J.L.; et al. AlGaN/GaN MIS-HFET with improvement in high temperature gate bias stress-induced reliability. In Proceedings of the 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), Waikoloa, HI, USA, 15-19 June 2014; pp. 55-58. [Google Scholar]

15. Man Ho, K.; Wong, K.Y.; Lin, Y.S.; Yao, F.W.; Tsai, M.W.; Chang, Y.C.; Chen, P.C.; Su, R.Y.; Wu, C.H.; Yu, J.L.; et al. CMOS-compatible GaN-on-Si field-effect transistors for high voltage power applications. In Proceedings of the 2014 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 15-17 December 2014; pp. 17.6.1-17.6.4. [Google Scholar]

16. Moens, P.; Banerjee, A.; Uren, M.J.; Meneghini, M.; Karboyan, S.; Chatterjee, I.; Vanmeerbeek, P.; Casar, M.; Liu, C.; Salih, A.; et al. Impact of buffer leakage on intrinsic reliability of 650V AlGaN/GaN HEMTs. In Proceedings of the 2015 International Electron Devices Meeting, Washington, DC, USA, 7-9 December 2015; pp. 35.2.1-35.2.4. [Google Scholar]

17. Bahl, S.R.; Joh, J.; Fu, L.; Sasikumar, A.; Chatterjee, T.; Pendharkar, S. Application reliability validation of GaN power devices. In Proceedings of the International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3-7 December 2016; pp. 20.5.1-20.5.4. [Google Scholar]

18. Koller, C.; Pobegen, G.; Ostermaier, C.; Pogany, D. Evidence of defect band in carbon-doped GaN controlling leakage current and trapping dynamics. In Proceedings of the 2017 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2-6 December 2017; pp. 33.4.1-33.4.4. [Google Scholar]

19. Meneghini, M.; Tajalli, A.; Moens, P.; Banerjee, A.; Stockman, A.; Tack, M.; Gerardin, S.; Bagatin, M.; Paccagnella, A.; Zanoni, E.; et al. Total suppression of dynamic-ron in AlGaN/GaN-HEMTs through proton irradiation. In Proceedings of the 2017 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2-6 December 2017; pp. 33.5.1-33.5.4. [Google Scholar]

20. Radhakrishna, U.; Lim, S.; Choi, P.; Palacios, T.; Antoniadis, D. GaNFET compact model for linking device physics, high voltage circuit design and technology optimization. In Proceedings of the 2015 International Electron Devices Meeting, Washington, DC, USA, 7-9 December 2015; pp. 9.6.1-9.6.4. [Google Scholar]

21. Cornigli, D.; Reggiani, S.; Gnani, E.; Gnudi, A.; Baccarani, G.; Moens, P.; Vanmeerbeek, P.; Banerjee, A.; Meneghesso, G. Numerical investigation of the lateral and vertical leakage currents and breakdown regimes in GaN-on-Silicon vertical structures. In Proceedings of the 2015 International Electron Devices Meeting, Washington, DC, USA, 7-9 December 2015; pp. 5.3.1-5.3.4. [Google Scholar]

22. Raciti, A.; Cristaldi, D.; Greco, G.; Vinci, G.; Bazzano, G. Integrated power electronics modules: Electro-thermal modeling flow and stress conditions overview. In Proceedings of the 2014 AEIT Annual Conference-From Research to Industry: The Need for a More Effective Technology Transfer (AEIT), Trieste, Italy, 18-19 September 2014; pp. 1-6. [Google Scholar]

23. Wong, K.Y.R.; Kwan, M.H.; Yao, F.W.; Tsai, M.W.; Lin, Y.S.; Chang, Y.C.; Chen, P.C.; Su, R.Y.; Yu, J.L.; Yang, F.J.; et al. A next generation CMOS-compatible GaN-on-Si transistors for high efficiency energy systems. In Proceedings of the 2015 International Electron Devices Meeting, Washington, DC, USA, 7-9 December 2015; pp. 9.5.1-9.5.4. [Google Scholar]

24. Di Cioccio, L.; Morvan, E.; Charles, M.; Perichon, P.; Torres, A.; Ayel, F.; Bergogne, D.; Baines, Y.; Fayolle, M.; Escoffier, R.; et al. From epitaxy to converters topologies what issues for 200 mm GaN/Si? In Proceedings of the 2015 International Electron Devices Meeting, Washington, DC, USA, 7-9 December 2015; pp. 16.5.1-16.5.4. [Google Scholar]

25. Hughes, B.; Chu, R.; Lazar, J.; Boutros, K. Increasing the switching frequency of GaN HFET converters. In Proceedings of the 2015 International Electron Devices Meeting, Washington, DC, USA, 7-9 December 2015; pp. 16.7.1-16.7.4. [Google Scholar]

26. Then, H.W.; Chow, L.A.; Dasgupta, S.; Gardner, S.; Radosavljevic, M.; Rao, V.R.; Sung, S.H.; Yang, G.; Fischer, P. High-K gate dielectric depletion-mode and enhancement-mode GaN MOS-HEMTs for improved OFF-state leakage and DIBL for power electronics and RF applications. In Proceedings of the 2015 International Electron Devices Meeting, Washington, DC, USA, 7-9 December 2015; pp. 16.3.1-16.3.4. [Google Scholar]

27. Coffa, S.; Saggio, M.; Patti, A. SiC- and GaN-based power devices: Technologies, products and applications. In Proceedings of the 2015 International Electron Devices Meeting, Washington, DC, USA, 7-9 December 2015; pp. 16.8.1-16.8.5. [Google Scholar]

28. Ishida, H.; Kajitani, R.; Kinoshita, Y.; Umeda, H.; Ujita, S.; Ogawa, M.; Tanaka, K.; Morita, T.; Tamura, S.; Ishida, M.; et al. GaN-based semiconductor devices for future power switching systems. In Proceedings of the International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3-7 December 2016; pp. 20.4.1-20.4.4. [Google Scholar]

29. Lidow, A.; Reusch, D.; Glaser, J. System level impact of GaN power devices in server architectures. In Proceedings of the International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3-7 December 2016; pp. 20.3.1-20.3.4. [Google Scholar]

30. Kumar, A.; De Souza, M.M. Extending the bounds of performance in E-mode p-channel GaN MOSHFETs. In Proceedings of the International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3-7 December 2016; pp. 7.4.1-7.4.4. [Google Scholar]

31. Nakazawa, S.; Shih, H.; Tsurumi, N.; Anda, Y.; Hatsuda, T.; Ueda, T.; Nozaki, M.; Yamada, T.; Hosoi, T.; Shimura, T.; et al. Fast switching performance by 20 A/730 V AlGaN/GaN MIS-HFET using AlON gate insulator. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2-6 December 2017; pp. 25.1.1-25.1.4. [Google Scholar]

32. Ji, D.; Gupta, C.; Chan, S.H.; Agarwal, A.; Li, W.; Keller, S.; Mishra, U.K.; Chowdhury, S. Demonstrating >1.4 kV OG-FET performance with a novel double field-plated geometry and the successful scaling of large-area devices. In Proceedings of the 2017 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2-6 December 2017; pp. 9.4.1-9.4.4. [Google Scholar]

33. Hwang, I.; Choi, H.; Lee, J.; Choi, H.S.; Kim, J.; Ha, J.; Um, C.-Y.; Hwang, S.-K.; Oh, J.; Kim, J.-Y.; et al. 1.6 kV, 2.9 mΩ cm² normally-off p-GaN HEMT device. In Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, Bruges, Belgium, 3-7 June 2012; pp. 41-44. [Google Scholar]

34. Sheu, J.K.; Su, Y.K.; Chi, G.C.; Jou, M.J.; Liu, C.C.; Chang, C.M.; Hung, W.C. Inductively coupled plasma etching of GaN using Cl₂/Ar and Cl₂/N₂ gases. J. Appl. Phys. 1999, 85, 1970-1974. [Google Scholar] [CrossRef]

35. Chiu, H.-C.; Chang, Y.-S.; Li, B.-H.; Wang, H.-C.; Kao, H.-L.; Hu, C.-W.; Xuan, R. High-Performance Normally off p-GaN Gate HEMT with Composite AlN/Al0.17Ga0.83N/Al0.3Ga0.7N Barrier Layers Design. IEEE J. Electron Devices Soc. 2018, 6, 201-206. [Google Scholar] [CrossRef]

36. Stockman, A.; Canato, E.; Tajalli, A.; Meneghini, M.; Meneghesso, G.; Zanoni, E.; Moens, P.; Bakeroot, B. On the origin of the leakage current in p-gate AlGaN/GaN HEMTs. In Proceedings of the 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, USA, 11-15 March 2018; pp. 4B.5-1-4B.5-4. [Google Scholar]

37. Hatano, M.; Taniguchi, Y.; Kodama, S.; Tokuda, H.; Kuzuhara, M. Reduced gate leakage and high thermal stability of AlGaN/GaN MIS-HEMTs using ZrO₂/Al₂O₃gate dielectric stack. Appl. Phys. Express 2014, 7, 044101. [Google Scholar] [CrossRef]

38. Sen, H.; Qimeng, J.; Shu, Y.; Chunhua, Z.; Chen, K.J. Effective Passivation of AlGaN/GaN HEMTs by ALD-Grown AlN Thin Film. IEEE Electron Device Lett. 2012, 33, 516-518. [Google Scholar]

39. Tsu-Yi, W.; Lin, S.-K.; Po-Wen, S.; Jian-Jiun, H.; Wei-Chi, C.; Chih-Chun, H.; Ming-Ji, T.; Yeong-Her, W. AlGaN/GaN MOSHEMTs With Liquid-Phase-Deposited TiO₂ as Gate Dielectric. IEEE Trans. Electron Devices 2009, 56, 2911-2916. [Google Scholar]

40. Kanamura, M.; Ohki, T.; Imanishi, K.; Makiyama, K.; Okamoto, N.; Kikkawa, T.; Hara, N.; Joshin, K. Joshin High power and high gain AlGaN/GaN MIS-HEMTs with high-k dielectric layer. Phys. Stat. Sol. 2008, 5, 2037-2040. [Google Scholar]

41. Dong Seup, L.; Chung, J.W.; Wang, H.; Xiang, G.; Shiping, G.; Fay, P.; Palacios, T. 245-GHz InAlN/GaN HEMTs with Oxygen Plasma Treatment. IEEE Electron Device Lett. 2011, 32, 755-757. [Google Scholar]

42. Ronghua, W.; Guowang, L.; Laboutin, O.; Cao, Y.; Johnson, W.; Snider, G.; Fay, P.; Jena, D.; Huili, X. 210-GHz InAlN/GaN HEMTs With Dielectric-Free Passivation. IEEE Electron Device Lett. 2011, 32, 892-894. [Google Scholar]

43. Bajaj, S.; Akyol, F.; Krishnamoorthy, S.; Hung, T.-H.; Rajan, S. Simulation of Enhancement Mode GaN HEMTs with Threshold> 5 V using P-type Buffer. arXiv, 2015; arXiv:1511.04438. [Google Scholar]

44. Wong, H.Y.; Braga, N.; Mickevicius, R.; Gao, F.; Palacios, T. Study of AlGaN/GaN HEMT degradation through TCAD simulations. In Proceedings of the 2014 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama, Japan, 9-11 September 2014; pp. 97-100. [Google Scholar]

45. Rashmi; Kranti, A.; Haldar, S.; Gupta, R.S. An accurate charge control model for spontaneous and piezoelectric polarization dependent two-dimensional electron gas sheet charge density of lattice-mismatched AlGaN/GaN HEMTs. Solid-State Electron. 2002, 46, 621-630. [Google Scholar]

46. Bakeroot, B.; Stockman, A.; Posthuma, N.; Stoffels, S.; Decoutere, S. Analytical Model for the Threshold Voltage of ${p}$ -(Al)GaN High-Electron-Mobility Transistors. IEEE Trans. Electron Devices 2018, 65, 79-86. [Google Scholar] [CrossRef]

47. Huang, H.; Liang, Y.C.; Samudra, G.S.; Huang, C.-F. Design of novel normally-off AlGaN/GaN HEMTs with combined gate recess and floating charge structures. In Proceedings of the IEEE 10th International Conference on Power Electronics and Drive Systems (PEDS), Kitakyushu, Japan, 22-25 April 2013; pp. 555-558. [Google Scholar]

# data[].attributes.attachment_link.title
A Comprehensive Review of Recent Progress on GaN High Electron Mobility Transistors: Devices, Fabrication and Reliability

# data[].attributes.attachment_link.description
GaN based high electron mobility transistors (HEMTs) have demonstrated extraordinary features in the applications of high power and high frequency devices. In this paper, we review recent progress in AlGaN/GaN HEMTs, including the following sections. First, challenges in device fabrication and optimizations will be discussed.

# data[].attributes.headline
Two-dimensional semiconductor transistors and integrated circuits for advanced technology nodes

# data[].attributes.subject
Two-dimensional semiconductor transistors and integrated circuits for advanced technology nodes

# data[].attributes.body
En este artículo se revisan los avances recientes en el desarrollo de transistores de semiconductores bidimensionales y su integración en circuitos, haciendo énfasis en técnicas para minimizar la resistencia de contacto y mejorar la movilidad de los portadores. Se exploran materiales como el grafeno, MoS2 y WS2. Los semiconductores 2D son muy interesantes ya que permiten una reducción significativa en el tamaño de los transistores, lo que es crucial para la fabricación de dispositivos más compactos y eficientes de cara a la era tecnológica en la que vivimos.

Andres Mateo Chilito Avella :)

# data[].attributes.attachment_link.readable_text
Two-dimensional (2D) semiconductors, particularly transition metal dichalcogenides, exhibit high mobility within atomic-scale thickness, immunity to short-channel effects, and back-end-of-the-line (BEOL) compatibility with complementary metal-oxide-semiconductor (CMOS) technology. These attributes have sparked substantial interest in extending the semiconductor roadmap beyond silicon. Major companies including TSMC, Intel, Samsung and IMEC have allocated substantial resources to research into, and development of, 2D-semiconductor technology for advanced technology nodes. The identification of the present development stage and the future target is vital to expedite the transition of 2D semiconductor technology from laboratory to production line. This perspective aims to provide a concise survey of the current progress and future direction of high-performance field-effect transistors (FETs) and integrated circuits (ICs) based on 2D semiconductors.

The International Roadmap for Devices and Systems (IRDS) projects the introduction of 2D semiconductors as channel materials in 0.7 nm nodes in 2034, in a highly scaled three-dimensional (3D) device architecture (Fig. 1a). The basic building block comprises a vertical complementary field-effect transistor (CFET) with gate-all-around (GAA) geometry (Fig. 1b), featuring a gate length of 12 nm and contacted gate pitch (CGP) of 38 nm [ 1]. Here, CGP denotes the minimal separation between neighboring device gates. Prototype devices, such as multi-bridge channel (MBC) FETs [ 2], CFETs utilizing 2D semiconductors [ 3], and MoS ₂ back-gate FETs with a contact pitch as small as 42 nm [ 4], have been reported. However, their fabrication processes present challenges for scalable and CMOS-compatible production, and their device performance falls short of the IRDS requirements due to unresolved issues in metal contact, dielectric integration, doping, spacer design, etc.

Contact resistance ( R c) determines the on-state current of transistors, particularly for short-channel devices. Various methods, such as semimetal contacts [ 5], 2D van der Waals contacts and Y-doping-induced phase-transition contact [ 6], have recently been proposed to notably reduce R c of 2D semiconductors. Particularly, the semimetal Sb (01|$\bar{1}$|2) contact achieved a remarkably low R c of 42 Ω·μm in monolayer MoS ₂ through orbital hybridization [ 5]. This value surpasses that of chemically bonded contact in bulk semiconductors and is within a factor of ∼2 from the quantum limit at a carrier density of |$3.0 \times {10}^{13}$| cm −2. The improved contact results in a current density of 1.23 mA/μm under 1 V source-drain bias. Despite achieving ultralow R c, several significant challenges for future IC application remain unresolved. A crucial consideration is the contact length ( L c), the overlap between metal electrode and channel, and determining the injection efficiency of charge carriers. Often, low R c values are achieved by utilizing L c on the micrometer scale. However, in advanced technology nodes, IRDS specifications require L c to be sub-20 nm. Although edge contacts with L c as short as 1 nm are feasible, their corresponding R c still exceeds 10 kΩ·μm. Additionally, conventional R c measurements employ a back-gate device structure to establish highly doped contact. Such a device structure, however, introduces parasitic capacitance arising from the overlap between gate and source/drain and will limit the high-frequency performance in circuits. Hence, it is imperative to incorporate spacer design into the structure of 2D semiconductor devices for effectively mitigating parasitic effects, specifically the undesired capacitance and resistance that arise from the interactions between the gate, substrate and source-drain.

In silicon CMOS, the contact and spacer regions undergo heavy doping with a concentration ranging from 10 ²¹ to 10 ²² cm −3 to reduce access resistance while keeping parasitic capacitance low, thereby reducing the resistive-capacitive (RC) delay of the transistor [ 1]. Consequently, it is imperative to develop controlled and reliable doping techniques for constructing transistors and ICs using 2D semiconductors. Currently, the most promising doping methods [ 7] include substitutional doping and surface charge-transfer doping. Substitutional doping involves the addition of external donor or acceptor elements during material synthesis, which has the potential to produce p- and n-type materials in batch fabrication. However, the reduced screening in 2D semiconductors leads to much larger dopant ionization energy, thus much lower doping efficiency than bulk semiconductors. Surface charge-transfer doping offers a gentle approach that preserves the structure of 2D materials. CMOS-compatible dopants mainly consist of non-stoichiometric oxides and nitrides, such as SiO x, AlO x, MoO x and SiN x. By employing photolithography, the spatially selective doping of 2D materials becomes achievable, and beneficial for realizing the ideal integrated device structure in Fig. 1b. Yet, these non-stoichiometric oxides might introduce additional long-range optical phonon scattering, and achieving precise control of the doping level remains challenging. Although the recently reported remote modulation doping method addresses this concern to some degree, it appears incompatible for device scaling [ 8]. Reliable and effective doping methods for 2D semiconductors are still to be developed.

The integration of ultrathin dielectrics in 2D semiconductor devices has experienced remarkable advancements in recent years. From the utilization of organic molecules as an interface buffer layer [ 9] to the adoption of self-oxidized Bi ₂OSe ₅ [ 10], the equivalent oxide thickness (EOT) has already met IRDS requirements for a sub-1 nm node. However, the interface trap density ( D it) at the dielectric-2D interface still exceeds that of the Si-SiO ₂ interface (<10 ¹⁰ cm −2) by ∼2 orders of magnitude. This discrepancy primarily stems from lattice defects and interface impurities, potentially leading to high power dissipation and reliability issues. It is worth noting that the utilization of in-situ oxidation to generate a high-κ oxide has the potential to produce an atomically sharp interface [ 11], akin to Si-SiO ₂. However, devices reported in existing experiments exhibit elevated subthreshold swing (SS) values exceeding 100 mV/dec. The precise control of oxidation conditions, while simultaneously avoiding adverse effects on the underlying 2D channel, continues to pose challenges. In addition, investigations into the reliability of gate dielectrics, a critical factor for industry, remain relatively limited. Besides single-device studies, conducting statistical analyses of yield and uniformity through measurements on multi-batch wafer-level arrays is also essential.

Although significant progress has been made in the performance enhancement of 2D transistors, the integration density of 2D ICs remains low. For example, a 1-bit microprocessor utilizing MoS ₂ transistors was successfully demonstrated [ 12], featuring 115 transistors in an area of 0.6 mm². In comparison, state-of-the-art CMOS-based CPUs possess over 10 billion transistors in ∼100 mm ². This substantial gap is attributed to the immaturity of highly crystalline 2D semiconductor materials, the manufacturing process of device integration and circuit design environment (Fig. 1c). These areas all necessitate continuous research and development by academia and industry.

For materials, the production of large (up to 12-inch) wafer-scale single-crystalline 2D semiconductor materials still poses a significant challenge, although proof-of-concept demonstration of 2-inch MoS ₂, MoSe ₂ and WS ₂ single crystals has been reported [ 13]. Key considerations include meticulous substrate engineering, growth thermodynamics and kinetics, equipment design and process control. To achieve success in this field, it is crucial to engage in iterative processes throughout the growth process and prioritize the development of specialized equipment, distinct from the commonly employed tube furnaces found in academic laboratories. Besides, a viable wafer-scale, non-destructive transfer technology is required to relocate 2D materials from growth substrate to integration platform in an ultra-clean environment. Ideally, this technique should take place in a vacuum.

To facilitate the lab-to-fab transition of 2D semiconductors, there is an urgent need for the advancement of standard device-integration processes tailored for large-scale manufacturing. Besides the aforementioned issues, processes related to the interconnection/stacking of 2D semiconductor transistors and circuits must also be developed, including etching, vias, thin film deposition, atomic layer deposition/etching, chemical mechanical polishing, passivation and encapsulation. It is important to highlight that all of these processes must meet stringent requirements, including compatibility with CMOS technology, as well as the prevention of structural damage and interface contamination in 2D semiconductors. Adopting a more forward-looking viewpoint, it is possible that growth, fabrication, integration equipment and systems operating within a high-vacuum environment might ultimately evolve into the optimal solution for the future manufacturing of 2D semiconductor ICs.

Circuit design plays a crucial role in Very Large-Scale Integration (VLSI). While some efforts have been dedicated to device-level modeling, there remains a lack of comprehensive circuit-level simulation tools that incorporate process design kits (PDKs) to assess circuit performance. Additionally, although many studies have provided statistical information regarding yield and variability [ 5], it is important to establish clear definitions of yield criteria and acceptable variability windows. Furthermore, addressing the challenges faced by 2D semiconductors in VLSI requires more than just design-related solutions; it necessitates the adoption of a design technology co-optimization (DTCO) methodology. Recently, we adopted DTCO to report the first gigahertz ring oscillator (RO) circuits based on air-gap MoS ₂ transistor design [ 14]. Looking forward, a process-aware DTCO approach is expected to yield a >40% improvement in the operating frequency performance of a 15-stage ring oscillator with a fan-out of 3 at 0.7 V supply in 2D-FET technology, as compared to silicon, at the IMEC 2 nm node [ 15].

FUNDING

This work was supported by the National Key R&D Program of China (2022YFB4400100, 2023YFF1500500, 2022YFA1402500 and 2021YFA0715600), the National Natural Science Foundation of China (T2221003, 62304101, 62341408 and 61927808), the Leading-Edge Technology Program of Jiangsu Natural Science Foundation (BK20232024, B20232001), the Jiangsu Province Key R&D Program (BE2023009-3), the Natural Science Foundation of Jiangsu Province (BK20230776), the China Postdoctoral Science Foundation (2022M711549 and 2022T15036), the Jiangsu Funding Program for Excellent Postdoctoral Talent (20220ZB63), the Fundamental Research Funds for the Central Universities, China, the Key Laboratory of Advanced Photonic and Electronic Materials, and the Collaborative Innovation Center of Solid-State Lighting and Energy-Saving Electronics. The authors would like to express their sincere gratitude to the Interdisciplinary Research Center for Future Intelligent Chips (Chip-X) and Yachen Foundation for their invaluable support. X.W. acknowledges the support by the New Cornerstone Science Foundation through the XPLORER PRIZE. W.L. acknowledges the support by the Xiaomi Foundation.

Conflict of interest statement. None declared.

REFERENCES

# data[].attributes.attachment_link.title
Two-dimensional semiconductor transistors and integrated circuits for advanced technology nodes

# data[].attributes.attachment_link.description
This Perspective aims to provide a concise survey of current progress and outlook future directions in high-performance transistors and integrated circuits

# data[].attributes.headline
Q&A: How advanced chip packaging can help redesign the future of semiconductors

# data[].attributes.subject
Q&A: How advanced chip packaging can help redesign the future of semiconductors

# data[].attributes.body
Este artículo se centra en el papel crucial del empaquetado avanzado de chips en la industria de semiconductores, destacando su importancia para mantener la evolución tecnológica y cumplir con los pronósticos de Moore's Law. Este enfoque implica el diseño y producción de semiconductores que consumen menos energía pero ofrecen mayor capacidad de procesamiento, lo que representa un avance significativo en la fabricación de dispositivos electrónicos más eficientes y potentes. Instituciones como Penn State, a través de iniciativas como el Centro para la Integración Heterogénea de Sistemas Micro Electrónicos (CHIMES), desempeñan un papel fundamental en la promoción de avances en la integración y empaquetado de chips, lo que impulsa la innovación y el desarrollo en la industria.

El empaquetado avanzado de chips se convierte en un elemento esencial para optimizar el rendimiento de los sistemas electrónicos, al permitir la integración de múltiples tecnologías en dispositivos compactos y rentables. Además de mantener el ritmo de Moore's Law, el empaquetado avanzado busca maximizar la eficiencia energética, el rendimiento, la fiabilidad y la asequibilidad de los sistemas, lo que impulsa la creación de dispositivos electrónicos más sofisticados y accesibles para los consumidores. Al colaborar con la industria y otras instituciones académicas, iniciativas como CHIMES de Penn State buscan traducir los avances en conocimiento en una próspera ecología de fabricación de chips en la región del Atlántico Medio, promoviendo la innovación y el desarrollo tecnológico en la industria de semiconductores.

Veronica Garcia Castro

# data[].attributes.attachment_link.readable_text
Credit: Unsplash/CC0 Public Domain

The phrase "advanced chip packaging" might conjure images of a fancy Pringles can. For those who manufacture semiconductors-also known as integrated circuits, chips or microchips-it represents a new frontier, a race to design and mass produce the next generation of semiconductors that use less energy while delivering more computing power.

Traditionally completed near the end of the manufacturing process, chip packaging is the arranging and installation of a chip with its electrical and protective components on a "substrate," or base plate, made of silicon or other materials.

Penn State plays a leading role in America's push for advancement in chips packaging as the home of the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), a partnership of 15 universities to initiate advances in chip integration and packaging.

Additionally, several Penn State researchers are focused on the topic, including Madhavan Swaminathan, department head of electrical engineering, William E. Leonhard Endowed Chair in the School of Electrical Engineering and Computer Science and director of CHIMES; and Daniel Lopez, Liang Professor of Electrical Engineering, director of the Penn State Nanofabrication Lab and the founder of the Mid-Atlantic Semiconductors Hub.

In a Q&A with Penn State News, Swaminathan and Lopez, both affiliated with the Penn State Materials Research Institute, discussed the future of chip manufacturing and advanced packaging and how Penn State-led initiatives like CHIMES and MASH help turn innovations in the lab into reliable domestic production.

A guiding principle in chip manufacturing is Moore's Law, which predicted that the number of transistors that can be packed in an integrated circuit would double every 18 months, resulting in smaller but more powerful semiconductors. Is this still achievable over the next decade?

Swaminathan: The main driver behind Moore's law is economics. The cost of a transistor used to be seven bucks in the early 1960s. Today, the cost of the transistor is one nano dollar-one-billionth of a dollar. The only item you can probably purchase for a nano dollar is a transistor. This has been the result of Moore's law.

The shrinkage of the transistor over the years has allowed more transistors to be integrated on a single chip and has enabled the increase in performance of systems they enable. However, recently we have reached an inflection point where the cost of the transistor is beginning to rise due to the cost of the equipment and processes used to shrink the transistor any further, and that is where packaging comes in. Advanced packaging is a means to continue Moore's law, where systems of the future can continue to be economical while the performance continues to increase.

How will advanced packaging techniques help in this regard?

Swaminathan: There are five important metrics that drive system development: power, performance, size, cost and reliability. Future systems need to consume less power, which translates into energy savings for our planet. The computational speeds of systems need to continuously increase to enable the solution to difficult problems in a reasonable time, also referred to as performance. The size of systems needs to be reduced, especially when mobility becomes important. And, of course, these systems need to be affordable and highly reliable as well. The role of advanced packaging becomes critical when all these metrics are considered simultaneously to optimize the system attributes.

Let's apply that to something commonplace, like a cell phone. Could you describe a typical chip architecture and how advanced packaging techniques could be applied in the manufacturing process?

Swaminathan: Ask yourself "what does a smart phone do today?" It allows you to communicate, compute and sense. All these functions are enabled through the creation, manipulation and processing of data. It turns out that the types of transistors required to support the three functions are not the same. In fact, the transistor technologies required are so disparate that these transistors cannot be combined on a single chip. In addition, supporting each of these functions may require separate chips as well-for example, memory chips that enable the storage of data different from the processor chips.

These chips need to be connected to each other, along with other non-transistor components, to build the smart phone. Since smart phones are cost-sensitive and size is an important attribute, these need to be considered as well. All this is enabled through advanced packaging that allows signals to be transmitted back and forth between chips while the chips consume minimal power. As the chips generate heat, packaging efficiently removes the heat while protecting the transistors from environmental conditions such as vibration, shock, temperature, humidity and other factors.

Lopez: In addition to the electronic components, a modern smart phone could have as many as 30 micro-mechanical sensors. These sensing elements, known as micro-electromechanical systems (MEMS), are vibrating structures smaller than the diameter of a human hair. They are used to measure time, speed, location and orientation of the phone, and they are critical components in the cell phone's microphones and cameras. Since MEMS-based sensors must interact with the environment, packaging them requires special structures, materials and processes that are not always compatible with the packages used for transistors.

Today's smart cell phone architectures are spectacular examples of the integration of multiple technologies in a device, but much more research is still needed to optimize the integration processes and the performance of multi-component systems.

CHIMES helps take advanced packaging a step further in the manufacturing process through heterogenous integration. What is that and how does it build on advanced packaging techniques?

Swaminathan: Heterogeneous Integration refers to connecting chips from different process technologies on a package to maximize the power, performance, size, cost and reliability of the overall system. Since these chips can originate at different fabrication facilities, the time to design and bring them to market can be reduced.

Such an approach requires the development of new system concepts, transistor devices, various electronic and photonic components such as antennas, capacitors, inductors, waveguides, new materials for the efficient transmission of signals and heat removal, chips communicating with each other side by side and on top of each other, and many more. This is the focus of CHIMES, where our metrics are driven based on emerging applications and a 10-year outlook.

Last fall, the $3 billion National Advanced Packaging Manufacturing Program (NAPMP) was announced to drive U.S. leadership in advanced packaging and stimulate a domestic semiconductor manufacturing presence. This spring, MASH held a workshop focused on the topic with the program's director, Subu Iyer, as the keynote speaker. What was the key takeaway from that workshop?

Swaminathan: NAPMP has two major goals: to establish American leadership by onshoring advanced packaging here in the United States, supported by a resilient supply chain, and to enable education and workforce development in advanced packaging. The key technological drivers to achieve the former is scale-in-reducing the dimensions of the wires in the package such that they are comparable to wiring on-chip-and scale-out-increasing the size of packages so that they become comparable in size to printed circuit boards. The combination of the two will help blur the interface between what is on-chip and off-chip, a need that heterogeneous integration helps address.

Lopez: With respect to the latter, education and workforce development goals need to be broad, and that includes reaching K-12 students, those in two-year colleges, veterans, people with disabilities, and those in four-year and advanced degree programs. The MASH workshop provided a unique forum to discuss these topics and resulted in multiple working groups that are currently developing solutions to many of the problems described above. The working groups include experts from academia, industry and government.

In 2021, the federal government passed the CHIPS Act (Creating Helpful Incentives to Produce Semiconductors for America) aimed at boosting semiconductor manufacturing in the United States. How are MASH and CHIMES helping to translate the knowledge generated by Penn State and partner institutions into a thriving chip manufacturing ecosystem in the Mid-Atlantic region?

Swaminathan: Universities are excellent in pre-competitive research, with some excelling in applied research as well. Industry, on the other hand, operates in a competitive world, especially in manufacturing. There is a big disconnect between the two sides, where innovations in the university laboratories are often lost and do not make it into manufacturing. This gap is often referred to as the "valley of death." This is exactly what we hope to correct through CHIMES and MASH, by introducing translational work through prototyping and piloting.

Prototyping enables higher levels of integration at the University while piloting in an industry setting provides for achieving statistical significance prior to manufacturing. The handshake between the two can result in the "valley of death" becoming a "valley of opportunity."

Lopez: The academic and industrial organizations partnering with CHIMES and MASH provide access to a unique chip manufacturing ecosystem in the Mid-Atlantic region that we hope will revolutionize the future of electronics in the U.S. MASH and CHIMES are working together to design novel curriculum activities that expand opportunities for training for underrepresented minorities in STEM academic careers.

# data[].attributes.attachment_link.title
Q&A: How advanced chip packaging can help redesign the future of semiconductors

# data[].attributes.attachment_link.description
The phrase "advanced chip packaging" might conjure images of a fancy Pringles can. For those who manufacture semiconductors-also known as integrated circuits, chips or microchips-it represents a new frontier, a race to design and mass produce the next generation of semiconductors that use less energy while delivering more computing power.

# data[].attributes.headline
Simple superconducting device could dramatically cut energy use in computing, other applications

# data[].attributes.subject
Simple superconducting device could dramatically cut energy use in computing, other applications

# data[].attributes.body
:0 En MIT desarrollaron un diodo superconductor que mejora significativamente la eficiencia energética en sistemas de computación de alta potencia, ofreciendo una conducción de corriente con cero resistencia en una dirección. Este avance es notable por su simplicidad y su capacidad para operar a través de un amplio rango de temperaturas. Aunque inicialmente se pensó en aplicaciones en computación cuántica, la tecnología utilizada sugiere posibilidades más amplias para dispositivos superconductores eficientes y escalables. Este nuevo hallazgo nos abre cientos de posibilidades para crear productos e inventos asombrosos como ingenieros electrónicos.

Andres Mateo Chilito Avella.

# data[].attributes.attachment_link.provider_name
MIT News | Massachusetts Institute of Technology

# data[].attributes.attachment_link.readable_text
MIT scientists and their colleagues have created a simple superconducting device that could transfer current through electronic devices much more efficiently than is possible today. As a result, the new diode, a kind of switch, could dramatically cut the amount of energy used in high-power computing systems, a major problem that is estimated to become much worse. Even though it is in the early stages of development, the diode is more than twice as efficient as similar ones reported by others. It could even be integral to emerging quantum computing technologies.

The work, which is reported in the July 13 online issue of Physical Review Letters, is also the subject of a news story in Physics Magazine.

"This paper showcases that the superconducting diode is an entirely solved problem from an engineering perspective," says Philip Moll, director of the Max Planck Institute for the Structure and Dynamics of Matter in Germany. Moll was not involved in the work. "The beauty of [this] work is that [Moodera and colleagues] obtained record efficiencies without even trying [and] their structures are far from optimized yet."

"Our engineering of a superconducting diode effect that is robust and can operate over a wide temperature range in simple systems can potentially open the door for novel technologies," says Jagadeesh Moodera, leader of the current work and a senior research scientist in MIT's Department of Physics. Moodera is also affiliated with the Materials Research Laboratory, the Francis Bitter Magnet Laboratory, and the Plasma Science and Fusion Center (PSFC).

The nanoscopic rectangular diode - about 1,000 times thinner than the diameter of a human hair - is easily scalable. Millions could be produced on a single silicon wafer.
Toward a superconducting switch
Diodes, devices that allow current to travel easily in one direction but not in the reverse, are ubiquitous in computing systems. Modern semiconductor computer chips contain billions of diode-like devices known as transistors. However, these devices can get very hot due to electrical resistance, requiring vast amounts of energy to cool the high-power systems in the data centers behind myriad modern technologies, including cloud computing. According to a 2018 news feature in Nature, these systems could use nearly 20 percent of the world's power in 10 years.

As a result, work toward creating diodes made of superconductors has been a hot topic in condensed matter physics. That's because superconductors transmit current with no resistance at all below a certain low temperature (the critical temperature), and are therefore much more efficient than their semiconducting cousins, which have noticeable energy loss in the form of heat.

Until now, however, other approaches to the problem have involved much more complicated physics. "The effect we found is due [in part] to a ubiquitous property of superconductors that can be realized in a very simple, straightforward manner. It just stares you in the face," says Moodera.

Says Moll of the Max Planck Institute, "The work is an important counterpoint to the current fashion to associate superconducting diodes [with] exotic physics, such as finite-momentum pairing states. While in reality, a superconducting diode is a common and widespread phenomenon present in classical materials, as a result of certain broken symmetries."
A somewhat serendipitous discovery
In 2020 Moodera and colleagues observed evidence of an exotic particle pair known as Majorana fermions. These particle pairs could lead to a new family of topological qubits, the building blocks of quantum computers. While pondering approaches to creating superconducting diodes, the team realized that the material platform they developed for the Majorana work might also be applied to the diode problem.

They were right. Using that general platform, they developed different iterations of superconducting diodes, each more efficient than the last. The first, for example, consisted of a nanoscopically thin layer of vanadium, a superconductor, which was patterned into a structure common to electronics (the Hall bar). When they applied a tiny magnetic field comparable to the Earth's magnetic field, they saw the diode effect - a giant polarity dependence for current flow.

They then created another diode, this time layering a superconductor with a ferromagnet (a ferromagnetic insulator in their case), a material that produces its own tiny magnetic field. After applying a tiny magnetic field to magnetize the ferromagnet so that it produces its own field, they found an even bigger diode effect that was stable even after the original magnetic field was turned off.
Ubiquitous properties
The team went on to figure out what was happening.

In addition to transmitting current with no resistance, superconductors also have other, less well-known but just as ubiquitous properties. For example, they don't like magnetic fields getting inside. When exposed to a tiny magnetic field, superconductors produce an internal supercurrent that induces its own magnetic flux that cancels the external field, thereby maintaining their superconducting state. This phenomenon, known as the Meissner screening effect, can be thought of as akin to our bodies' immune system releasing antibodies to fight the infection of bacteria and other pathogens. This works, however, only up to some limit. Similarly, superconductors cannot entirely keep out large magnetic fields.

The diodes the team created make use of this universal Meissner screening effect. The tiny magnetic field they applied - either directly, or through the adjacent ferromagnetic layer - activates the material's screening current mechanism for expelling the external magnetic field and maintaining superconductivity.

The team also found that another key factor in optimizing these superconductor diodes is tiny differences between the two sides, or edges, of the diode devices. These differences "create some sort of asymmetry in the way the magnetic field enters the superconductor," Moodera says.

By engineering their own form of edges on diodes to optimize these differences - for example, one edge with sawtooth features, while the other edge not intentionally altered - the team found that they could increase the efficiency from 20 percent to more than 50 percent. This discovery opens the door for devices whose edges could be "tuned" for even higher efficiencies, Moodera says.

In sum, the team discovered that the edge asymmetries within superconducting diodes, the ubiquitous Meissner screening effect found in all superconductors, and a third property of superconductors known as vortex pinning all came together to produce the diode effect.

"It is fascinating to see how inconspicuous yet ubiquitous factors can create a significant effect in observing the diode effect," says Yasen Hou, first author of the paper and a postdoc at the Francis Bitter Magnet Laboratory and the PSFC. "What's more exciting is that [this work] provides a straightforward approach with huge potential to further improve the efficiency."

Christoph Strunk is a professor at the University of Regensburg in Germany. Says Strunk, who was not involved in the research, "the present work demonstrates that the supercurrent in simple superconducting strips can become nonreciprocal. Moreover, when combined with a ferromagnetic insulator, the diode effect can even be maintained in the absence of an external magnetic field. The rectification direction can be programmed by the remnant magnetization of the magnetic layer, which may have high potential for future applications. The work is important and appealing both from the basic research and from the applications point of view."
Teenage contributors
Moodera noted that the two researchers who created the engineered edges did so while still in high school during a summer at Moodera's lab. They are Ourania Glezakou-Elbert of Richland, Washington, who will be going to Princeton University this fall, and Amith Varambally of Vestavia Hills, Alabama, who will be entering Caltech.

Says Varambally, "I didn't know what to expect when I set foot in Boston last summer, and certainly never expected to [be] a coauthor in a Physical Review Letters paper.

"Every day was exciting, whether I was reading dozens of papers to better understand the diode phenomena, or operating machinery to fabricate new diodes for study, or engaging in conversations with Ourania, Dr. Hou, and Dr. Moodera about our research.

"I am profoundly grateful to Dr. Moodera and Dr. Hou for providing me with the opportunity to work on such a fascinating project, and to Ourania for being a great research partner and friend."

In addition to Moodera and Hou, corresponding authors of the paper are professors Patrick A. Lee of the MIT Department of Physics and Akashdeep Kamra of Autonomous University of Madrid. Other authors from MIT are Liang Fu and Margarita Davydova of the Department of Physics, and Hang Chi, Alessandro Lodesani, and Yingying Wu, all of the Francis Bitter Magnet Laboratory and the Plasma Science and Fusion Center. Chi is also affiliated with the U.S. Army CCDC Research Laboratory.

Authors also include Fabrizio Nichele, Markus F. Ritter, and Daniel Z. Haxwell of IBM Research Europe; Stefan Ilićof Materials Physics Center (CFM-MPC); and F. Sebastian Bergeret of CFM-MPC and Donostia International Physics Center.

This work was supported by the Air Force Office of Sponsored Research, the Office of Naval Research, the National Science Foundation, and the Army Research Office. Additional funders are the European Research Council, the European Union's Horizon 2020 Research and Innovation Framework Programme, the Spanish Ministry of Science and Innovation, the A. v. Humboldt Foundation, and the Department of Energy's Office of Basic Sciences.

# data[].attributes.attachment_link.keywords[]
mit plasma science and fusion center (psfc)

# data[].attributes.attachment_link.title
Simple superconducting device could dramatically cut energy use in computing, other applications

# data[].attributes.attachment_link.description
An MIT team created a simple superconducting device that could dramatically cut energy use in computing, among other important applications. The ultra-small "switch" could be easily scaled.

# data[].attributes.headline
Research Progress in Semiconductor Materials with Application in the Photocatalytic Reduction of CO2

# data[].attributes.subject
Research Progress in Semiconductor Materials with Application in the Photocatalytic Reduction of CO2

# data[].attributes.body
Este articulo nos muestra como la funcion de los semiconductores en la reducción fotocatalítica del CO2, una gran estrategia para combatir la contaminación por CO2 y la crisis energética. Los autores hacen un recorrido por los últimos avances en este campo, destacando la necesidad de desarrollar materiales semiconductores de alta eficiencia que posean estructuras con sitios catalíticos abundantes. Estos materiales no solo deben ser capaces de facilitar la reducción del CO2 sino también de hacerlo de manera eficiente aprovechando la energía solar, una fuente limpia y renovable, lo cual es realmente genial. Pero puntualmente se habla sobre como la modificación de las propiedades físicas, químicas y electrónicas de los catalizadores semiconductores puede marcar una diferencia significativa en su desempeño. Se examinan diversos tipos de semiconductores, incluyendo TiO2, MOFs, BiVO4, etc. Discutiendo sus limitaciones actuales como la baja eficiencia en la separación y migración de fotocarriers, y cómo las intervenciones específicas están abriendo camino hacia la mejora de la reducción fotocatalítica del CO2. Si se lograran desarrollar aún más estas investigaciones tendrían un asombroso impacto en el medio ambiente (aspecto que es muy relevante en la actualidad)

Andres Mateo Chilito Avella

# data[].attributes.attachment_link.readable_text
Jiangsu Key Laboratory of Atmospheric Environment Monitoring and Pollution Control, Collaborative Innovation Center of Atmospheric Environment and Equipment Technology, School of Environmental Science and Engineering, Nanjing University of Information Science & Technology, Nanjing 210044, China

Author to whom correspondence should be addressed.

1. Introduction

Over the past hundred years, the establishment and development of industrial civilization has promoted a profound transformation of human social productivity and created huge social wealth for mankind. In the process of industrial development, the annual increase in the consumption of fossil fuels, an important energy source for industrial development, has led to the degradation of the natural carbon cycle as well as a surge in atmospheric CO ₂ concentration [ 1, 2, 3, 4]. Especially in recent decades, due to the rapid population increase and the rapid development of industry, the CO ₂ produced by human respiration and fossil fuel combustion has far exceeded historical levels [ 5]. In addition, human development has led to ecological destruction, weakening the ability of Nature to absorb CO ₂ and resulting in increasing levels of CO ₂ in the atmosphere.

In recent years, studies on CO ₂ fixation and transformation have gradually developed. Adsorption, storage, reduction and conversion methods can reduce atmospheric CO ₂ concentration [ 6]. However, these methods achieve little, and they do not solve the fundamental problem. CO ₂ is a potential carbon resource, and its utilization is a promising way to reduce CO ₂ to fuel. Therefore, strategies for CO ₂ conversion have been developed. These reduction pathways include electrochemical reduction, photochemical reduction, and biotransformation [ 7, 8]. Photochemical reduction is the most promising method for CO ₂ conversion. It converts Nature's nearly unlimited solar energy into usable chemical energy, achieving the conversion and utilization of CO ₂ without consuming fossil energy. At the same time, solar energy is a clean and renewable resource.

In view of this, the conversion of CO ₂ to hydrocarbons is considered a forward-looking solution because it can solve both the energy problem and the environmental crisis [ 9, 10, 11, 12, 13]. In this regard, artificial photocatalytic reduction is one of the most promising solutions, and the use of this method to photocatalytically reduce CO ₂ into usable fuels has attracted special attention worldwide [ 14]. Various semiconductors, including TiO ₂ [ 15, 16, 17], MOFs [ 18, 19, 20], BiVO ₄ [ 21, 22, 23] and metal halide perovskites (MHPs) [ 24, 25, 26], have been used as photoreduction catalysts for CO ₂. Although these semiconductor photocatalysts have a wide band gap and can provide enough negative electrons for the photocatalytic reduction of CO ₂, most of them only respond to ultraviolet light (UV), which severely limits their use of light. In addition, these semiconductor photocatalysts usually have low photocarrier separation and migration efficiency [ 27, 28]. These problems greatly reduce the efficiency of photocatalytic CO ₂ reduction. Take the most commonly used TiO ₂ photocatalyst as an example. TiO ₂ photocatalysts have low electron mobility and poor adsorption activation capacity for CO ₂ reactants [ 29]. Therefore, much research has been devoted to various modifications to improve the efficiency of photocatalytic CO ₂ reduction. The transition metals cobalt and nickel are often used in the study of photocatalytic CO ₂ reduction due to their rich crustal content, high stability, low cost and high catalytic activity. Cobalt and nickel metal ions can also effectively avoid the generation of high-energy intermediates and promote the multi-electron reduction of CO ₂, so they are favorable components in photocatalytic CO ₂ reduction processes [ 30, 31, 32]. It has been reported that defect engineering can change the band structure and optical properties of semiconductor photocatalysts, thus improving the light absorption capacity of semiconductors and improving the carrier separation efficiency [ 33, 34, 35]. As one of the most efficient solutions, surface modification can optimize the surface atomic states, surface structures and charge properties of semiconductor photocatalysts, and is therefore a promising photocatalytic reaction technology [ 36, 37, 38]. Vu et al. [ 36] reviewed different oxide catalysts for CO ₂ reduction together with various structural engineering strategies (e.g., nanostructure engineering and heterostructure engineering). Each strategy was found to have its own advantages and disadvantages, so further adjustment is needed to further improve the performance of photocatalysts. For example, photocatalysts are modified with precious metals. These precious metals can play the role of modifier and provide more catalytic active sites for the photocatalytic reduction of CO ₂. Although these precious-metal modifiers can significantly improve the photoreduction performance of CO ₂, their rarity and high cost greatly affect their practical application [ 39, 40, 41, 42]. Therefore, it is necessary to develop non-noble metal or no-metal modified photocatalysts. Given the challenges and limitations of current solutions for photocatalytic CO ₂ reduction, it is of great significance to design novel photocatalysts to improve the photoreduction of CO ₂.

However, existing reviews on the photocatalytic reduction of CO ₂ by semiconductor materials are not comprehensive, and the recent research progress has not been sufficiently summarized. Therefore, this review summarizes the progress of research on semiconductor catalysts which have recently demonstrated excellent performance. In this paper, we review the effects of different types of semiconductor catalysts on the photocatalytic reduction of CO ₂. In addition, we summarize the mechanisms of photocatalytic CO ₂ reduction on these semiconductor catalyst. Finally, we discuss future development trends of semiconductor catalysts.

2. Semiconductor Materials for the Photocatalytic Reduction of CO₂

The photocatalytic reduction of CO ₂ is a surface/interface reaction. As discussed above, it is important to find and use raw materials which are environmentally friendly and effective as catalysts. In 1979, Inoue et al. [ 43] used semiconductor materials such as CdS, TiO ₂ and WO ₃ to reduce CO ₂ to CO, CH ₄ and other chemical. Figure 1 shows the band structures of different semiconductor photocatalysts. Currently known semiconductor photocatalyst materials for the photocatalytic reduction of CO ₂ include metal oxides (Co ₃O ₄, BiVO ₄, TiO ₂), metal chalcogenides (CdS, MoS ₂, SnS ₂), nitrides (g-C ₃N ₄), bismuth halide oxides (BiOCl, BiOBr) and bimetallic hydroxides (NiAl-LDH), among others. Although the photocatalysts mentioned above have been proven able to reduce CO ₂, they still have some disadvantages. For example, bismuth halide compounds have strong oxidation ability, but the bottom position of their conduction band is comparatively positive, and their reduction performance is not very good [ 44, 45]. Some photocatalysts have unstable chemical properties and are prone to photocorrosion during photocatalytic reaction, the products of which are toxic to the environment.

2.1. TiO₂ Photocatalyst

As an n-type semiconductor material, TiO ₂ is regarded as an ideal semiconductor material for environmental pollution control due to its good chemical stability, non-toxicity and environmental friendliness. It has great potential application value in the field of environment and energy [ 47]. In 1972, Fujishima and Honda reported [ 14] that TiO ₂ could decompose water molecules into hydrogen and oxygen under ultraviolet light, bringing extensive attention to TiO ₂ as a photocatalyst material. TiO ₂ has been widely used in the photocatalytic decomposition of decomposition of hydrogen in aquatic products [ 48, 49, 50], the degradation of pollutants [ 51, 52, 53], the reduction of CO ₂ [ 54, 55, 56, 57] etc., and a series of research achievements have been made. TiO ₂ photocatalyst materials are also very common in daily life; they are widely used in solar cells, coatings, cosmetics, antibacterial materials and air purifiers, as examples.

TiO ₂ can be found in the form of three crystal polymorphs: anatase, rutile and brookite [ 58]. The three crystals have a twisted octahedral structure of six oxygen atoms around a titanium atom. Anatase and rutile forms have tetragonal crystal structures. The different electronic structures of the three crystal types of TiO ₂ lead to great differences in their photocatalytic performance. Tang et al. [ 59] studied the effect of different crystal types on the photocatalytic performance of TiO ₂. It was found that the degradation rate of pollutants was nearly 100% when anatase or mixes with anatase and rutile forms was used as photocatalyst. The degradation rate was less than 15% when pure rutile TiO ₂ was used as photocatalyst. Jin et al. [ 60] prepared PbO-decorated TiO ₂ composites by a one-pot method with highly photoactive CO ₂ conversion, as shown in Figure 2. The heterojunction formed by the catalyst could effectively inhibit the recombination of photogenerated charge, while the PbO could improve the adsorption of CO ₂ on the catalyst. Therefore, the photocatalytic activity of the heterojunction complex for CO ₂ reduction was significantly improved.

Morphology is also an important factor affecting the photocatalytic performance of TiO ₂. The specific surface areas, active sites, charge transfer rates and exposed crystal surfaces of TiO ₂ catalysts with different morphologies are significantly different, leading to great differences in their performance. Cao et al. [ 61] prepared a TiO ₂ photocatalyst with nanorods and nanorod-hierarchical nanostructures. The catalyst had better photocatalytic performance for CO ₂ reduction than commercial TiO ₂ (P25). The high catalytic activity was mainly attributed to the improved charge transfer performance, specific surface area and light absorption performance of the catalyst lent by the nanorod-hierarchical nanostructures. Tan et al. [ 62] synthesized an Ag/Pd bimetal supported on a N-doped TiO ₂ nanosheet for CO ₂ reduction. Due to the modification of the Ag/Pd bimetal and the N doping, the absorption of visible light in the TiO ₂ nanosheets was improved. This system also provided abundant surface defects and oxygen vacancies for the TiO ₂ nanosheets, causing the catalyst to exhibit high performance for the photocatalytic reduction of CO ₂ to CH ₄. Kar et al. [ 63] prepared a TiO ₂ nanotube photocatalyst which showed a highly efficient photocatalytic reduction of CO ₂ to CH ₄. The high photocatalytic activity was mainly attributed to the enhancement of visible light absorption by the nanotube structure. In addition to the crystal size and morphology of TiO ₂ catalyst, the intensity of the external light source also has an effect on the photocatalytic activity of TiO ₂-generally, as the light intensity increases, more photogenerated electrons are generated by the catalyst's excitation, and the photocatalytic reaction is promoted as a result. Yang et al. [ 64] found that the photocatalytic degradation rate of TiO ₂ to paracetamol attenuated with the decrease of light intensity.

2.2. Co/Ni-Based Catalysts

The transition metals cobalt and nickel, which have various redox states, have been widely used in the study of photocatalytic CO ₂ reduction due to their rich crustal content, low cost, high catalytic activity for CO ₂ and strong adsorption capacity [ 65, 66, 67]. In 2015, Wang et al. [ 68] prepared Co-ZIF-9 by a solvothermal method for the study of photocatalytic CO ₂ reduction. The results showed that the three-dimensional MOFs structure of Co-ZIF-9 was beneficial for CO ₂ enrichment. The Co ²⁺ ions and imidazole groups played a synergistic role in the photocatalytic reduction of CO ₂. The Co ²⁺ ion was beneficial for electron transport, and the imidazole group was beneficial for the activation of CO ₂ molecules. Wang et al. [ 69, 70] also studied the photocatalytic CO ₂ reduction performance of cobalt-based spinel oxides. MnCo ₂O ₄ microspheres and ZnCo ₂O ₄ nanorods were prepared by solvothermal calcination and hydrothermal methods, respectively. The results showed that both catalysts exhibited excellent catalytic stability, which confirmed the possibility of Co-based spinel oxides for photocatalytic CO ₂ reduction. Zhang et al. [ 71] studied the performance of six Co-MOFs with different coordination environments applied to photocatalytic CO ₂ reduction, as shown in Figure 3. In pure CO ₂ atmosphere, the MAF-X27l-OH material had high CO selectivity (98.2%). When the relative pressure of CO ₂ dropped to 0.1 atm, the conversion rate of MAF-X27l-OH remained at about 80%, while the CO conversion rate of Co-MOF materials without this ligand decreased significantly. These results suggest that MAF-X27l-OH has excellent photocatalytic CO ₂ reduction performance. These conclusions provide a theoretical basis for future studies on the photocatalytic CO ₂ reduction of Co-based nanocatalysts.

In addition to Co-based nanomaterials, many Ni-based nanomaterials have also been applied in the study of photocatalytic CO ₂ reduction. Niu et al. [ 72] synthesized a spongy nickel-organic heterogeneous photocatalyst (Ni(TPA/TEG), which could effectively adsorb CO ₂. This novel Ni-based photocatalyst significantly inhibited the production of H ₂, CH ₄ and CH ₃OH during the photocatalytic reduction of CO ₂. Thus, efficient CO ₂ conversion was achieved, and the selectivity of CO was close to 100%. Yu et al. [ 73] obtained a covalent organic framework bearing single Ni sites (Ni-TpBpy) for the selective reduction of CO ₂ to CO. Figure 4 shows the photocatalytic CO ₂ reduction performance of Ni-TpBpy under visible light. The results showed that Ni-TpBpy effectively promoted the formation of CO in the reaction medium, and the selectivity of CO was 96% after 5 h of reaction. More importantly, the catalyst maintained 76% CO selectivity in a low CO ₂ atmosphere. Ni-TpBpy showed good photocatalytic performance for the selective reduction of CO ₂, which was mainly attributed to the synergistic effect of single Ni catalytic site and TpBpy supporter.

2.3. Metal Halide Perovskites (MHPs)

In recent years, metal halide perovskite (MHP) materials have become attractive in the field of optoelectronics and energy conversion [ 74]. Compared with traditional semiconductor nanocrystals, these materials have high extinction coefficient, narrow band emission, long carrier diffusion length and high defect tolerance. In addition, the diversity of perovskite structures also allows the band gap to be adjusted in order to enhance light capture [ 75]. The crystal structure of MHPs is similar to that of oxide perovskite. The chemical formula is ABX ₃, where A is a monovalent cation, B is a divalent metal cation (the most common are Pb ²⁺ and Sn ²⁺) and X is a halogen ion. MHP nanocrystals exhibit a halogen-rich surface structure. Perovskites can be classified as inorganic or organic-inorganic hybrid halogenated perovskites according to the type of cations in their chemical structure. The emergence of MHPs with unique photoelectric characteristics brings new opportunities for efficient photocatalytic CO ₂ reduction.

Since the reduction potential of MHPs for CO ₂ reduction usually changes with the nanocrystal size, the catalytic activity of MHP nanocrystals is also affected by their size. Sun et al. [ 76] first synthesized CsPbBr ₃ quantum dots of different sizes to study the effect of quantum dot size on CO ₂ reduction. It was found that CsPbBr ₃ with a diameter of 8.5 nm had the longest carrier lifetime, more negative band bottom potential and the highest catalytic activity. As shown in Figure 5, Xu et al. [ 77] designed CsPbBr ₃/GO composites by combining graphene oxide (GO) with CsPbBr ₃ and used them for photocatalytic CO ₂ reduction. The CsPbBr ₃/GO composites exhibited higher CO ₂ reduction activity than pure CsPbBr ₃ nanocrystals. It was found that the improved CO ₂ reduction performance was mainly attributed to the existence of efficient charge transfer in CsPbBr ₃/GO composites, and charge injection graphene oxide effectively promoted the charge injection from MHPs to GO. Other studies have shown that the catalytic activity of MHPs can be improved by coupling various modifiers with MHPs nanocrystals. Man et al. [ 78] used NH x-rich porous g-C ₃N ₄ nanosheets (PCNs) to stabilize CsPbBr ₃ nanocrystals. The formation of a N-Br bond leads to close contact with g-C ₃N ₄ nanocrystals and CsPbBr ₃ nanocrystals. In order to suppress the serious charge recombination in MHPs, Jiang et al. [ 79] designed a novel Z-scheme alpha-Fe ₂O ₃/amine-RGO/CsPbBr ₃ catalyst for high-efficiency CO ₂ reduction. The construction of the Z-scheme heterojunction promoted charge separation and retained strong reducing electrons in CsPbBr ₃ as well as strong oxidation holes in α-Fe ₂O ₃. Finally, it promoted the activity of artificial photosynthesis.

2.4. Metal-Organic Frameworks (MOFs)

Metal-organic framework materials (MOFs) are organic-inorganic hybrid materials with intramolecular pores formed by self-assembly between inorganic metal ions or clusters and organic ligands through coordination bonds. MOFs' large specific surface area, high porosity and tunable structure make them energy storage materials with strong development potential. The structure of MOFs can be controlled by changing the central metal atoms and the interaction between different organic ligands. Transition metals such as Fe, Co and Ni are often selected as central metal sources. As the raw materials of MOFs, such transition metals are abundant, widely distributed and easily available on Earth, which to some extent makes the raw materials cost of MOFs low. Therefore, MOFs are widely used in catalytic energy conversion and other applications [ 80]. In photocatalytic processes, MOFs can be used as photocatalysts or modifiers to promote the photocatalytic reaction.

MOFs are a relatively new type of frame material, and their uniformly dispersed metal nodes are conducive to the adsorption and activation of gas molecules. The combination of semiconductors and MOFs to form inorganic-organic nanocomposites can not only satisfy the absorption of photons by semiconductor materials to generate carriers, but also enable the materials to adsorb and activate highly stable CO ₂ molecules. Xiong et al. [ 81] developed a method for synthesizing Cu ₃(BTC) ₂@TiO ₂ core-shell structures. The loose shell structure of TiO ₂ facilitates the passage of CO ₂ molecules through the shell, while the strong CO ₂ absorption of Cu ₃(BTC) ₂ in the core favors the efficient CO ₂ reduction of nanocomposites. Wu et al. [ 82] designed and constructed inorganic perovskite quantum dots and organic MOF complexes. A series of MAPbI(3)@PCN-221(Fe-x) composite photocatalytic materials were prepared by encapsulating quantum dots in MOF channels by a deposition method. In the aqueous phase, the MAPbI(3)@PCN-221(Fe-0.2) composite structure showed a high photocatalytic activity for CO ₂-much higher than that of PCN-221(Fe-0.2). At the same time, hole oxidation oxidized H ₂O to O ₂ to achieve the total decomposition of CO ₂. Alvaro et al. [ 83] reported that MOF-5 produced by the coordination of Zn ²⁺ and terephthalic acid has semiconductor-like properties. There is an electron-hole separation and transfer process in which electrons migrate from ligand to adjacent metal nodes for the photocatalytic degradation of phenol. Subsequently, a great deal of research was conducted on the construction and development of MOFs with semiconductor properties. On the one hand, MOFs act as light absorbers. On the other hand, due to their unique structural characteristics, they can be used as highly efficient catalysts integrating light absorption and catalytic active sites [ 84]. Fang et al. [ 85] designed and synthesized a pyrazolyl porphyrinic Ni-MOF (PCN-601) with active sites of light capture exposure and high specific surface area, as shown in Figure 6. The experimental results showed that PCN-601 had high-efficiency CO ₂ photoreduction performance under the condition of CO ₂-saturated water vapor. Under the condition of simulated solar irradiation (AM 1.5 G), the CH ₄ yield of PCN-601 reached 92 μmol·h −1·g −1 and the apparent quantum yield (AQY) of CH ₄ was 2.18%. Therefore, the accumulated research suggests that MOFs have the best interfacial charge transfer and kinetic process among the materials evaluated for photocatalytic CO ₂ reduction. The optimal catalytic activity was obtained in the catalytic reaction system, which provided a new direction for guiding and controlling the synthesis of new MOF materials.

2.5. Other Semiconductor Photocatalysts

Compared with commonly used photocatalysts (MHPs, MOFs, TiO ₂, etc.), other efficient photocatalytic materials for the reduction of CO ₂ need to be developed and studied. The conduction band position of SiC has a comparatively more negative potential, which can produce photogenerated electrons with stronger reduction ability for the photocatalytic reduction of CO ₂. However, the synthesis of SiC in a high-temperature protective atmosphere is not conducive to the regulation of its nanostructure [ 86, 87]. Layered double hydroxides (LDHs) such as Zn-Al LDH [ 88], Mg-Al LDH [ 89] and Zn-Cu-Ga LDH [ 90] have been used for the photocatalytic reduction of CO ₂. Teramura et al. [ 91] synthesized a variety of LDHs with surface alkaline sites for the photocatalytic conversion of CO ₂ to CO. Their activities tend to be higher than that of pure hydroxide. Graphite carbon nitride (g-C ₃N ₄) is a metal-free polymer material considered to be a promising visible-light catalyst [ 92, 93]. Hsu et al. [ 94] used graphene oxide as a catalyst for the efficient photocatalytic conversion of CO ₂ to methanol, and synthesized a graphene catalyst with an improved method to improve the activity. The yield of CH ₃OH was six times that obtained using pure TiO ₂. The photocatalytic activity of highly porous Ga ₂O ₃ for the reduction of CO ₂ was found to be more than four times that of commercial Ga ₂O ₃ without the need for additives [ 95]. The performance of porous Ga ₂O ₃ was improved by doubling the surface area and tripling the adsorption capacity. Tanaka et al. [ 96] used H ₂ instead of H ₂O as a reducing agent to photocatalytically reduce CO ₂ on Ga ₂O ₃, and the product was CO instead of CH ₄. Notably, nearly 7.3% of the surface-adsorbed CO ₂ was converted.

An effective strategy is to develop new semiconductor photocatalysts with visible-light response to improve the utilization rate of sunlight, so as to obtain higher photocatalytic activity. Zhou et al. [ 97] prepared Bi ₂WO ₆ square nanoplates by a hydrothermal method, and the product obtained by reducing CO ₂ was CH ₄. Figure 7 shows the result of CH ₄ formation on Bi ₂WO ₆ photocatalysts. Cheng et al. [ 98] successfully prepared hollow Bi ₂WO ₆ microspheres, and methanol was obtained by reducing CO ₂. Xi et al. [ 99] prepared W ₁₈O ₄₉ nanowires by a one-step liquid-phase method. Under visible-light irradiation, CO ₂ was photocatalytically reduced in water vapor to generate CH ₄. The average formation rate of CH ₄ was significantly increased by using Pt and Au as cocatalysts.

3. Principle of the Photocatalytic Reduction of CO₂

3.1. Process of the Photocatalytic Reduction of CO₂

Among many catalytic technologies, green and cheap semiconductor photocatalytic technology provides a new approach to the realization of this process. The inspiration for the semiconductor photocatalytic reduction of CO ₂ comes from the photosynthesis of green plants in Nature. In Nature, plants absorb solar energy to convert CO ₂ and H ₂O into organic matter and release oxygen to sustain their growth. Artificial photosynthesis using synthetic photocatalysts is used to simulate natural photosynthesis and reduce CO ₂ into chemical products with high added value using sunlight. This is the most promising environment-friendly technology for CO ₂ reduction at present.

Figure 8 shows a diagram of the mechanism of photocatalytic CO ₂ reduction using semiconductor materials [ 100]. It can be seen from the figure that the photocatalytic reduction of CO ₂ by semiconductor materials involves three basic processes. First, when the semiconductor photocatalyst is irradiated by incident light with an energy greater than or equal to its band gap (E.g.), the electrons in the valence band are excited and transition to the conduction band to form excited-state electrons with strong reduction ability. Holes with strong oxidation capacity equal to the number of electrons are left in the valence band, thus forming electron-hole pairs. The electrons and holes are then transferred to the surface of the semiconductor catalyst. Finally, the electrons reduce the CO ₂ molecules on the surface of the catalyst, and the holes convert the H ₂O molecules on the surface of the catalyst into O ₂. Most of the photogenerated electrons and holes recombine because the recombination rate of electrons and holes is much faster than the rate of surface redox reactions. Energy is released as light or heat, and only a small fraction of the electrons/holes can reach the surface of the catalyst to participate in the redox reaction. Therefore, it is very important to improve the separation efficiency of electrons and holes in the photocatalytic reduction of CO ₂.

3.2. Types of Photocatalytic CO₂ Reduction

The H ₂O molecule is an ideal reducing agent for the reduction of CO ₂, providing protons to consume holes and producing oxygen and hydrogen during the reaction. At present, most photocatalytic CO ₂ reduction reactions need to build reaction systems based on H ₂O molecules. The reaction system mainly includes two types, namely, gas-solid and liquid-solid systems. Figure 9 shows schematics of gas-solid and liquid-solid systems for photocatalytic CO ₂ reduction.

In a gas-solid system, the H ₂O molecule is present as water vapor and the catalyst is uniformly dispersed at the bottom of the reactor or uniformly coated on the substrate and placed at the bottom of the reactor. CO ₂ gas flows into the reactor as a continuous stream or exists in the closed off-line system as a saturated gas. Zhang et al. [ 101] found that if TiO ₂ nanotubes supported by Pt were used as photocatalyst, methane production increased when the concentration of water around the catalyst and the surface -OH group was relatively high. However, when Pt-TiO ₂ nanoparticles were used as catalyst, the CO ₂/H ₂O ratio had no effect on methane production. This indicates that the adsorption energy of water molecules on the catalyst surface affects the activity of the gas-phase photocatalytic system. Due to the microporous structure and surface properties of the materials, the adsorption of CO ₂ and H ₂O on the active sites leads to different photocatalytic processes and the formation of different products [ 102].

In a liquid-solid system, the catalyst is suspended in an aqueous solution. Before the reaction, CO ₂ gas is bubbled into the water to reach the saturation state [ 103]. The yield of product when using H ₂O as reducing agent is very low. It was found that adding triethanolamine or isopropanol into the solution consumes holes to improve the efficiency of photocatalytic CO ₂ reduction. Kaneco et al. [ 104] used TiO ₂ to photocatalytically reduce CO ₂ in isopropanol solution. The CO ₂ was reduced to methane, and isopropanol was oxidized to acetone. Another factor with a great influence on the reaction system is the suspension pH. Alkaline substances (NaOH, NaHCO ₃, etc.) are usually added to the solution to improve the solubility of CO ₂ and promote the reduction of CO ₂ [ 105]. The pH of the suspension decreased from about 14 to 7.5, indicating that the solution mainly contained HCO ₃− and a small amount of CO ₃ 2−, which could have accelerated the photocatalytic reduction of CO ₂. The OH − ions in alkaline solution can be used as strong hole-trapping agents to improve photocatalytic activity. Wu et al. [ 106] significantly increased the yield of CH ₃ OH by adding NaOH solution to the photocatalytic system solution. In addition, the addition of electrolytes increased total production as well as C2 products such as ethanol and acetaldehyde.

The difference between the gas-solid and liquid-solid systems mainly lies in the different concentrations of CO ₂ and H ₂O on the surface of the catalyst; the products under different concentrations are also different. The disadvantage of gas-solid systems is that the contact area between reactants and catalyst is small, while the disadvantage of liquid-solid systems is that a large number of H ₂O molecules occupy adsorption sites for CO ₂. Therefore, different optimization designs of catalysts are needed for different reaction systems in order to overcome the defects of the reaction system itself and maximize the efficiency of photocatalytic CO ₂ reduction.

3.3. Reaction Conditions of Photocatalytic CO₂ Reduction

Photocatalytic reactions are usually influenced by external environmental and operational conditions, such as the wavelength range and intensity of light, the quality of the catalyst, the pH value of the solution, the pressure of CO ₂, the reducing agent and the temperature. Hou et al. [ 107] studied the influence of different irradiation sources in the photocatalytic reduction of CO ₂ with Au nanoparticle/TiO ₂ catalyst, and generated different products such as CH ₄, CO, CH ₃OH and HCHO. It was found that the photocatalytic reduction product of aqueous CO ₂ by Au nanoparticle/TiO ₂ catalyst under different excitation wavelengths (λ = 532 nm, 254 nm and 365 nm) was CH ₄. However, additional reaction products (including C ₂H ₆, CH ₃OH and HCHO) were observed under UV light (254 nm mercury lamp). The photocatalytic activity and selectivity can also be effectively improved by increasing the concentration of CO ₂. Mizuno et al. [ 108] reported that with the increase of CO ₂ pressure, the adsorption rate of hydrogen on the TiO ₂ surface gradually exceeded that of CO ₂. This adsorbed hydrogen began to form low-mass hydrocarbons such as CH ₄ and CH ₂CH ₂. In gas-phase systems, increasing the pressure of CO ₂ and water vapor can also promote the binding of reactants at the active sites of the catalyst, thus improving the photocatalytic activity of CO ₂ reduction [ 101]. A further variable that must be considered in the photocatalytic reduction processes is the system temperature. Fox and Dulay believed that a small temperature change had little effect on the photocatalytic reaction [ 109]; however, high temperature not only increases the collision frequency and diffusivity, but also increases the rate of thermal activation steps. Guan et al. [ 110] used a Pt-loaded K ₂Ti ₆O ₁₃ photocatalyst combined with an Fe-based catalyst to reduce CO ₂ and water vapor under sunlight and high temperature. It was found that the yield of HCOOH, CH ₃OH and C ₂H ₅ OH increased significantly with the increase of reaction temperature.

The crystal phase structure of the catalyst must also be considered. If the structure is the same but the exposed crystal plane is different, the photocatalytic CO ₂ reduction performance will be different. Yamashita et al. [ 111] studied the photocatalytic CO ₂ reduction by TiO ₂ single crystal with rutile phase, exposed to (100) and (110) surfaces. They found that the activity of the (100) surface was significantly higher than that of the (110) surface, and CH ₄/CH ₃OH products could be detected in the TiO ₂ system exposed to the (100) surface. It can be concluded that optimizing the microstructure of catalytic materials can significantly improve the photocatalytic CO ₂ reduction activity.

4. Conclusions and Perspectives

Since the first Industrial Revolution, with the increasing frequency of human activities and the massive burning of fossil fuels, the emission of CO ₂ into the atmosphere has been increasing. This will lead to global warming, sea level rise, land desertification and other extreme climate and environmental problems. At the same time, the rapid development of industry has led to sharp increases in energy consumption worldwide. However, as non-renewable resources, fossil energy reserves are very limited. The development of new renewable energy sources is currently an urgent need of human society. One promising strategy for the mitigation of negative effects brought by CO ₂ emissions is to simulate natural photosynthesis and use clean and sustainable solar energy to convert CO ₂ into hydrocarbon fuels with added value; this could simultaneously alleviate environmental pollution and energy shortage in today's human society. However, because CO ₂ is a symmetrical linear molecule and carbon is in its highest oxidation state, it has high thermodynamic stability, making the process of CO ₂ reduction by visible light extremely challenging.

Many studies have been published on the development and design of efficient photocatalysts to achieve photocatalytic CO ₂ reduction, but the photocatalytic reduction conversion efficiency is far from sufficient to meet the needs of practical application. This is usually caused by the high recombination rate of photogenerated electron-hole pairs and the poor adsorption activation capacity of CO ₂ molecules in photocatalytic CO ₂ reduction processes. In order to solve the bottleneck problem of low CO ₂ adsorption activation capacity in the process of CO ₂ photoreduction, it is necessary to modify the catalyst. There are many common catalytic material modification methods, such as morphology control, surface microstructure control and grain size control.

In the future, the research focus of semiconductor catalysts for the photocatalytic reduction of CO ₂ should still be on improving the efficiency of photocatalytic reduction of CO ₂. The main research direction should be the development of new semiconductor catalysts and optimized reaction conditions. In addition, the study of the reaction mechanism and type of photocatalytic reduction of CO ₂ on semiconductor catalysts is helpful to find ways to improve the catalyst activity. Meanwhile, optimizing the reaction path is of great significance for the large-scale synthesis of catalysts in the future industrialization process. From an economic perspective, Co/Ni-based catalysts have the lowest cost among the catalysts (TiO ₂ photocatalyst, Co/Ni-based catalysts, MHPs, MOFs and other semiconductor photocatalysts) mentioned in this review, while MHP catalysts are relatively expensive. Finally, in order to achieve green catalysis, the preparation cost of the catalyst must be considered, and the catalyst should be applied to the industrial photocatalytic reduction of CO ₂ through improved reactors and other methods.

Author Contributions

Conceptualization, M.C. and Y.C.; formal analysis, P.G.; investigation, Y.C.; resources, M.C.; data curation, P.G.; writing-original draft preparation, Y.C.; writing-review and editing, L.X.; funding acquisition, M.C. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the National Natural Science Foundation of China (grant number 21976094, 22176100) and the National Key Research and Development Project 9 (grant number 2018YFC0213802).

Conflicts of Interest

The authors declare no conflict of interest.

References

1. Varga, B.; Vida, G.; Varga-Laszlo, E.; Hoffmann, B.; Veisz, O. Combined Effect of Drought Stress and Elevated Atmospheric CO₂ Concentration on the Yield Parameters and Water Use Properties of Winter Wheat (Triticum aestivum L.) Genotypes. J. Agron. Crop. Sci. 2017, 203, 192-205. [Google Scholar] [CrossRef]

2. Vermeer, M.; Rahmstorf, S. Global Sea Level Linked to Global Temperature. Proc. Natl. Acad. Sci. USA 2009, 106, 21527-21532. [Google Scholar] [CrossRef] [PubMed] [Green Version]

3. Habisreutinger, S.N.; Schmidt-Mende, L.; Stolarczyk, J.K. Photocatalytic Reduction of CO₂ on TiO₂ and Other Semiconductors. Angew. Chem. Int. Ed. 2013, 52, 7372-7408. [Google Scholar] [CrossRef] [PubMed]

4. Cai, J.; Shen, F.; Shi, Z.; Lai, Y.; Sun, J. Nanostructured TiO₂ for Light-Driven CO₂ Conversion into Solar Fuels. APL Mater. 2020, 8, 040914. [Google Scholar] [CrossRef] [Green Version]

5. Wang, X.; Wang, Y.; Gao, M.; Shen, J.; Pu, X.; Zhang, Z.; Lin, H.; Wang, X. BiVO₄/Bi₄Ti₃O₁₂ Heterojunction Enabling Efficient Photocatalytic Reduction of CO₂ with H₂O to CH₃OH and CO. Appl. Catal. B Environ. 2020, 270, 118876. [Google Scholar] [CrossRef]

6. Yang, H.; Teng, F.; Gu, W.; Liu, Z.; Zhao, Y.; Zhang, A.; Liu, Z.; Teng, Y. A Simple Post-Synthesis Conversion Approach to Zn(OH)F and the Effects of Fluorine and Hydroxyl on the Photodegradation Properties of Dye Wastewater. J. Hazard. Mater. 2017, 333, 250-258. [Google Scholar] [CrossRef] [PubMed] [Green Version]

7. Shen, Y.; Ren, F.; Liu, H. Progress in Research on Photocatalytic Performance of Doped-TiO₂. Rare Met. Mater. Eng. 2006, 35, 1841-1844. [Google Scholar]

8. Rao, Z.; Shi, G.; Wang, Z.; Mahmood, A.; Xie, X.; Sun, J. Photocatalytic Degradation of Gaseous Vocs over Tm³⁺-TiO₂: Revealing the Activity Enhancement Mechanism and Different Reaction Paths. Chem. Eng. J. 2020, 395, 125078. [Google Scholar] [CrossRef]

9. Feizpoor, S.; Habibi-Yangjeh, A.; Seifzadeh, D.; Ghosh, S. Combining Carbon Dots and Ag₆Si₂O₇ Nanoparticles with TiO₂: Visible-Light-Driven Photocatalysts with Efficient Performance for Removal of Pollutants. Sep. Purif. Technol. 2020, 248, 116928. [Google Scholar] [CrossRef]

10. Nguyen, T.P.; Nguyen DL, T.; Nguyen, V.H.; Le, T.H.; Vo DV, N.; Trinh, Q.T.; Bae, S.-R.; Chae, S.Y.; Kim, S.Y.; Le, Q.V. Recent Advances in TiO₂-Based Photocatalysts for Reduction of CO₂ to Fuels. Nanomaterials 2020, 10, 337. [Google Scholar] [CrossRef] [Green Version]

11. Niu, K.; Xu, Y.; Wang, H.; Ye, R.; Xin, H.L.; Lin, F.; Tian, C.; Lum, Y.; Bustillo, K.C.; Doeff, M.M.; et al. A Spongy Nickel-Organic CO₂ Reduction Photocatalyst for Nearly 100% Selective CO Production. Sci. Adv. 2017, 3, 1700921. [Google Scholar] [CrossRef] [PubMed] [Green Version]

12. Ou, M.; Tu, W.; Yin, S.; Xing, W.; Wu, S.; Wang, H.; Wan, S.; Zhong, Q.; Xu, R. Amino-Assisted Anchoring of CsPbBr₃ Perovskite Quantum Dots on Porous g-C₃N₄ for Enhanced Photocatalytic CO₂ Reduction. Angew. Chem. Int. Ed. 2018, 57, 13570-13574. [Google Scholar] [CrossRef]

13. Jiang, Y.; Liao, J.-F.; Chen, H.-Y.; Zhang, H.-H.; Li, J.-Y.; Wang, X.-D.; Kuang, D.-B. All-Solid-State Z-Scheme Alpha-Fe₂O₃/Amine-RGO/CsPbBr₃ Hybrids for Visible-Light-Driven Photocatalytic CO₂ Reduction. Chem 2020, 6, 766-780. [Google Scholar] [CrossRef]

14. Tsuneoka, H.; Teramura, K.; Shishido, T.; Tanaka, T. Adsorbed Species of CO₂ and H₂ on Ga₂O₃ for the Photocatalytic Reduction of CO₂. J. Phys. Chem. C 2010, 114, 8892-8898. [Google Scholar] [CrossRef]

Figure 1. Band structures of some representative photocatalysts. Reprinted with permission from Ref. [ 46]. 2020 Xu, Q.; Zhang, L.; Cheng, B.; Fan, J.; Yu, J.

Figure 3. TOF values for the photocatalytic reduction of CO ₂ to CO at 1.0 atm (blue) and 0.1 atm (orange). Reprinted with permission from Ref. [ 71]. 2018 Wang, Y.; Huang, N.-Y.; Shen, J.-Q.; Liao, P.-Q.; Chen, X.-M.; Zhang, J.-P.

Figure 4. ( a) Comparison of the free energy of CO ₂ reduction to CO with and without TpBpy ligand; ( b) proposed mechanism for the photocatalytic CO ₂ reduction by Ni-TpBpy. Reprinted with permission from Ref. [ 73]. 2019 Zhong, W.; Sa, R.; Li, L.; He, Y.; Li, L.; Bi, J.; Zhuang, Z.; Yu, Y.; Zou, Z.

Figure 5. Schematic of photocatalytic CO ₂ reduction over CsPbBr ₃QDs/GO. Reprinted with permission from Ref. [ 77]. 2017 Xu, Y.-F.; Yang, M.-Z.; Chen, B.-X.; Wang, X.-D.; Chen, H.-Y.; Kuang, D.-B.; Su, C.-Y.

Figure 6. Proposed mechanism for CO ₂ photoreduction by PCN-601 with (a) charge separation and transfer through a coordination sphere; (b) reaction pathways for the products. Reprinted with permission from Ref. [ 85]. 2020 Fang, Z.-B.; Liu, T.-T.; Liu, J.; Jin, S.; Wu, X.-P.; Gong, X.-Q.; Wang, K.; Yin, Q.; Liu, T.-F.; Cao, R.

Figure 8. Schematic of the photocatalytic reduction of CO ₂ by semiconductor materials. Reprinted with permission from Ref. [ 100]. 2016 Li, K.; Peng, B.; Peng, T.

Figure 9. Schematics of gas-solid ( a) and liquid-solid ( b) systems for photocatalytic CO ₂ reduction.

Publisher's Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

# data[].attributes.attachment_link.title
Research Progress in Semiconductor Materials with Application in the Photocatalytic Reduction of CO2

# data[].attributes.attachment_link.description
The large-scale burning of non-renewable fossil fuels leads to the gradual increase of the CO2 concentration in the atmosphere, which is associated with negative impacts on the environment. The consequent need to reduce the emission of CO2 resulting from fossil fuel combustion has led to a serious energy crisis.

# data[].attributes.headline
Recent progress in single-molecule transistors: their designs, mechanisms and applications

# data[].attributes.subject
Recent progress in single-molecule transistors: their designs, mechanisms and applications

# data[].attributes.body
Este artículo nos muestra el desarrollo de transistores de molécula única. Destacando su potencial para transformar la tecnología mediante dispositivos ultra miniaturizados. Además, se explora cómo estos transistores funcionan, se diseñan y las posibles aplicaciones futuras, como la computación avanzada y almacenamiento de energía eficiente. Aunque esto suena muy chévere, aún hay desafíos por afrontar como la precisión del ensamblaje molecular y la estabilidad, mientras se resalta el potencial para innovaciones futuras principalmente en nanotecnología. Este campo nos abre como ingenieros electrónicos nuevas posibilidades para la electrónica a escala atómica, prometiéndonos grandes avances en la velocidad y eficiencia de los dispositivos.

Andres Mateo Chilito Avella.

# data[].attributes.attachment_link.title
Recent progress in single-molecule transistors: their designs, mechanisms and applications

# data[].attributes.attachment_link.description
Single-molecule field-effect transistors (FETs) are the key building blocks of future electronic circuits. At the same time, they are also a unique platform for studying physical mechanisms at the single-molecule level. How to construct single-molecule FETs and how to efficiently control the charge transfer

# data[].attributes.body
Esta noticia muestra un interesante desarrollo colombiano en tecnología e innovación. Se muestra que el Grupo de Investigación sobre Nuevos Materiales (GINUMA) de la Universidad Pontificia Bolivariana (UPB) en alianza con la famosa empresa de pinturas Pintuco hacen este aporte que busca mejorar las telecomunicaciones vía Wi-Fi de los espacios recubiertos con esta nueva pintura. No solamente es una mejora en el área de materiales de las telecomunicaciones sino que también abre la puerta a desarrollos en diferentes ámbitos; se mencionan algunos como: alimentos, ingeniería civil, textiles e, incluso, en la medicina.

# data[].attributes.attachment_link.readable_text
La Universidad Pontificia Bolivariana, los investigadores del programa de Ingeniería en nanotecnología, en alianza con la empresa Pintuco están desarrollando un proyecto que le apuesta a crear una pintura que, además de decorar, tenga una funcionalidad tecnológica para los hogares y empresas.

La universidad explica que el objetivo es aprovechar las ondas de radiofrecuencia que genera el router que proporciona la señal Wi-fi para potenciar la señal de internet, con un recubrimiento que se comportará como un amplificador en las pinturas.

Puede leer: La mente del trol, más agresiva por elecciones

Docentes y estudiantes que hacen parte del Grupo de Investigación sobre Nuevos Materiales (GINUMA), en conjunto con la Unidad de Investigación y Desarrollo de Pintuco, ya desarrollaron el primer prototipo de esta pintura.

Herbert Enrique Kerguelén Grajales, coordinador del programa académico de pregrado en Ingeniería Textil y Nanotecnología e investigador principal de este proyecto, explicó: "vislumbramos que efectivamente al formular la pintura con nanotecnología podemos lograr un aumento en la señal de radiofrecuencia".

Actualmente el equipo de investigadores se encuentra definiendo los sistemas en escala nanométrica que se pueden utilizar para esa aplicación, de modo que más adelante se puedan suministrar las nanopartículas para que Pintuco formule y fabrique el recubrimiento dentro de su compañía.

Lea también: Gobierno nacional expide Decreto que actualiza topes de espectro

Por su parte, Marleny Yepes Duque ingeniera química y gerente senior de Desarrollo e Investigación en Pintuco, aseguró que la alianza con la UPB es clave porque sus estudios les permiten a Pintuco incluir nuevas funcionalidades en los productos.

Investigadores indicaron que los recubrimientos pueden ser adaptados en las pinturas, también en la electrónica, en los alimentos o bebidas energéticas, en la ingeniería civil, textiles e, incluso, en la medicina, mejorando la manera en la que se tratan algunas enfermedades o se crean tratamientos médicos basados en la medicina de precisión.

Más noticias: Esta es la falla en 'Instagram Stories' que obliga a repetir visualización

Además, afirman que la incorporación de partículas de tamaño nanométrico en productos como el champú, filtros solares, los televisores o en los helados, puede alterar sus propiedades forma significativa y generar diversos beneficios.

Como ejemplo, también hablaron del oro, el cual es un gran conductor eléctrico, pero en la nanoescala resulta ser un sensor químico útil para detectar encimas, hormonas y servir como sistema para la detección del cáncer.

También puede leer:
Así puede instalar iOS 16 en iPhone antes de su lanzamiento oficial Lo que dice Google de su inteligencia artificial supuestamente consciente
TECNÓSFERA
Twitter: @TecnosferaET

# data[].attributes.attachment_link.title
Pintura que puede ayudar a mejorar red Wi-fi fue creada en Colombia

# data[].attributes.attachment_link.description
El proyecto está en manos de investigadores del programa de Ingeniería en Nanotecnología de la UPB.

# data[].attributes.body
En un trabajo en conjunto investigadores de University of Illinois Urbana-Champaign, the National Energy Technology Laboratory, Oak Ridge National Laboratory and the Taiwan Semiconductor Manufacturing Company, han desarrollado una técnica de manufactura de transistores de tres capas atómicas de espesor, usando como materia prima carbón mineral. Lo novedoso de este nuevo proceso es la posibilidad de crear nano electrónica en 2D y el buen rendimiento mecánico y eléctrico de los productos finales.

Fuente: https://www.nature.com/articles/s44172-023-00141-9

Herney David Vega Duarte

# data[].attributes.attachment_link.title
Ultrathin quasi-2D amorphous carbon dielectric prepared from solution precursor for nanoelectronics - Communications Engineering

# data[].attributes.attachment_link.description
Fufei An and colleagues report a solution-based strategy to prepare large-area, freestanding amorphous quasi-2D carbon nanomembranes from coal-derived carbon dots. Their mechanical and dielectric properties make these attractive materials for applications in nanoelectronic devices such as memristors and 2D-based transistors.

# data[].attributes.headline
Primer semiconductor de Grafeno funcional

# data[].attributes.subject
Primer semiconductor de Grafeno funcional

# data[].attributes.body
Como se puede observar en la noticia, investigadores del Georgia Institute of Technology, al dopar el semimetal se le modifican las propiedades, para que este se comporte como un semiconductor. Los investigadores afirman que tiene una variedad de ventajas sobre los semiconductores 2D, ya que este contiene una mayor velocidad de la movilidad de electrones, una estructura atómica más robusta y menores perdidas energética por calor. En el ámbito de la Electrónica Digital, este material representa un notable progreso con respecto al silicio, potencialmente dando lugar a una nueva generación de procesadores y dispositivos electrónicos. No obstante, es necesario esperar, así, evaluar si este material sintético logrará cumplir con las exigencias industriales y la eficacia que el silicio ha demostrado en la industria.

Hernando José Díaz Beltrán

# data[].attributes.attachment_link.readable_text
Epitaxial graphene could cause a paradigm shift in the field of electronics and allow for completely new technologies that take advantage of its unique properties. The material allows the quantum mechanical wave properties of electrons to be utilized, which is a requirement for quantum computing.

"Our motivation for doing graphene electronics has been there for a long time, and the rest was just making it happen," de Heer said. "We had to learn how to treat the material, how to make it better and better, and finally how to measure the properties. That took a very, very long time."

According to de Heer, it is not unusual to see yet another generation of electronics on its way. Before silicon, there were vacuum tubes, and before that, there were wires and telegraphs. Silicon is one of many steps in the history of electronics, and the next step could be graphene.

"To me, this is like a Wright brothers moment," de Heer said. "They built a plane that could fly 300 feet through the air. But the skeptics asked why the world would need flight when it already had fast trains and boats. But they persisted, and it was the beginning of a technology that can take people across oceans."

Citation: Zhao, J. et al. Ultrahigh-mobility semiconducting epitaxial graphene on silicon carbide. Nature (2024).

DOI: https://doi.org/10.1038/s41586-023-06811-0

Writer: Catherine Barzler

Video and Photos: Chris McKenney

#####

The Georgia Institute of Technology, or Georgia Tech, is one of the top public research universities in the U.S., developing leaders who advance technology and improve the human condition. The Institute offers business, computing, design, engineering, liberal arts, and sciences degrees. Its more than 45,000 undergraduate and graduate students, representing 50 states and more than 148 countries, study at the main campus in Atlanta, at campuses in France and China, and through distance and online learning. As a leading technological university, Georgia Tech is an engine of economic development for Georgia, the Southeast, and the nation, conducting more than $1 billion in research annually for government, industry, and society.

# data[].attributes.attachment_link.title
Researchers Create First Functional Semiconductor Made From Graphene

# data[].attributes.attachment_link.description
Researchers at the Georgia Institute of Technology have created the world's first functional semiconductor made from graphene, a single sheet of carbon atoms held together by the strongest bonds known. Semiconductors, which are materials that conduct electricity under specific conditions, are foundational components of electronic devices.

# data[].attributes.headline
Tin perovskite transistors and complementary circuits based on A-site cation engineering

# data[].attributes.subject
Tin perovskite transistors and complementary circuits based on A-site cation engineering

# data[].attributes.body
Como podemos ver en el artículo se presenta un avance que considero bien importante/interesante en la creación de transistores de perovskita de estaño, utilizando una técnica especial de ingeniería de cationes (es decir usar química para mejorar propiedades de los materiales, más que nada semiconductores). Esta técnica está permitiendo fabricar transistores de muy alta calidad, según el artículo con propiedades sobresalientes como alta movilidad de huecos y excelentes relaciones de corriente de encendido/apagado. Estos transistores los podemos comparar con los dispositivos comerciales actuales y al realizar esta comparación, es asombrosa la promesa de económica y bajo consumo energético que ofrecen. Este desarrollo seguro tendrá un impacto significativo en nuestras vidas que gira en torno a los semiconductores como hemos visto desde la primera clase y así se abrirán posibilidades para crear dispositivos electrónicos más eficientes.

Andres Mateo Chilito Avella.

# data[].attributes.attachment_link.readable_text
The development and commercialization of high-performance n-type metal oxide field-effect transistors have outpaced their p-type counterparts1,2. Tin (Sn ²⁺) halide perovskites, such as caesium tin triiodide (CsSnI ₃) and methylammonium tin triiodide (MASnI ₃), are p-type semiconductors with high hole mobilities (several hundreds of square centimetres per volt per second) and excellent processability via cost-effective, scalable and low-temperature film deposition methods3,4,5,6,7,8. Their dispersive valence band maximum and small hole carrier effective mass (comparable with that of silicon) provide good intrinsic hole transport properties. As a result, tin perovskites are promising semiconductors for the development of high-performance p-channel transistors, which could be used with n-channel metal oxide transistors to create noise-immune and low-power-consumption complementary-metal-oxide-semiconductor-like electronics9,10,11.

The development of high-performance tin perovskite thin-film transistors (TFTs) requires the fabrication of high-quality tin perovskite semiconductor films. However, tin perovskites typically show fast film crystallization, which leads to defective films and uncompetitive device performance12,13. B- and X-site engineering (Pb and Br/Cl alloying) can slow down Sn-I perovskite crystallization, yielding uniform films with dense grains and low defects14,15. Perovskite TFTs fabricated with this approach can deliver encouraging electrical performance with high field-effect mobility ( μ FE) of up to around 50 cm ² V −1 s −1. However, the involvement of heavy Pb and strong ionic Br/Cl raises concerns about Pb toxicity and enhances Fröhlich interactions between the charge carriers and electric fields produced by phonons, limiting charge-carrier mobilities at room temperature3.

Intrinsically, Sn/I as B-/X-site components can benefit high hole mobilities due to the strong Sn5 s-I5 p coupling near the valence band maximum and weak Fröhlich interaction3. In contrast, the A-site cation has a less direct influence on the band edge but can assist crystallization, adjust the tolerance factor, contribute to entropic/structural stabilization and indirectly optimize the perovskite properties16,17. Previous efforts, including using mixed A cations for core-shell structures and designing more conducting bulky organic spacers, have improved TFT performance, but the maximum μ FE value is less than 25 cm ² V −1 s −1 (refs. 6,7,11). In this Article, we show that the A cations of caesium-formamidinium-phenethylammonium (CsFAPEA) can be used to create high-quality cascaded pure-Sn-channel films and a low-defect phase-pure perovskite/dielectric interface. The optimized TFTs exhibit a hole mobility of over 70 cm ² V −1 s −1 and a current ratio ( I on/ I off) exceeding 10 ⁸, which is similar to commercial low-temperature polysilicon (LTPS) device performance.

The Sn perovskite thin films (~30 nm thickness) with different A-cation compositions were deposited onto dielectric silicon oxide (SiO ₂; 100 nm thickness) substrates from different precursors using spin coating, followed by gold source and drain electrode evaporation, creating the bottom-gate top-contact TFTs (Fig. 1a). The different precursors, which mainly contain desired A-cation compositions and tin(ii) iodide (SnI ₂) were prepared in a glove box and all the preparation details are given in Methods. We use the nomenclature of FA, FAPEA and CsFAPEA to denote all the perovskite compounds, which act as the semiconducting layers in the TFTs with optimized performance per type. Pristine FA devices show conductor behaviours with a negligible field effect and I on/ I off (Supplementary Fig. 1a). Such phenomena result from the high background hole density of three-dimensional (3D) Sn perovskites, due to the lowest formation energy of Sn-vacancy defects18,19. We then involved PEA cations, which can tune the crystallization process of FASnI ₃ perovskite, reducing the defect densities20,21. The FAPEA TFTs (made from the optimal molar ratio of FA:PEA = 7:2) show clear field-effect modulation with an average μ FE value of 14 cm ² V −1 s −1 and I on/ I off of 2.5 × 10 ⁷ (Supplementary Fig. 1a). To explore the feasibility for higher and competitive TFT performance, we further involved the third Cs cation to substitute the partial FA cations.

a, Structural scheme of the Sn perovskite TFT. The arrow depicts the charge-carrier transport path. b, μ FE and I on/ I off of TFTs based on channels fabricated from mixed precursors with different Cs molar ratios, the x in (CsxFA 1-x) ₇PEA ₂. The error bars are calculated from ten devices per type, and data are presented as mean ± standard deviation. c, d, Transfer ( c) and output ( d) characteristics of the optimized TFTs (Cs ratio = 10 mol%). I g in c indicates the gate leakage current. The | I DS| 1/2 versus V GS data of the forward scan are shown in the blue linear line, corresponding to the right y axis. V DS = −40 V. Channel width/length = 1,000 μm/200 μm. Supplementary Fig. 4 shows the electrode geometry. e, Transfer characteristics of 50 individual CsFAPEA TFTs fabricated from ten different batches. The inset shows the μ FE statistics. f, Representative μ FE values of reported perovskite TFTs based on different channel films. LTPS, low-temperature polysilicon level ( μ FE ≈ 70 cm ² V −1 s −1, I on/ I off ≈ 10 ⁷).

Surprisingly, the triple-cation-engineered TFTs show notably boosted performance, and 10 mol% Cs substitution delivers the optimal improvement, including a fivefold higher μ FE and tenfold higher I on/ I off compared with those of pristine FAPEA TFTs (Fig. 1b). Either a lower or higher Cs ratio decreases μ FE and I on/ I off and results in noticeable dual-sweep hysteresis (Supplementary Fig. 1b). The typical p-channel transfer characteristics of an optimized CsFAPEA TFT (denoting (CsxFA 1-x)PEA ₂Sn ₈I ₂₅, x = 10%) are shown in Fig. 1c, exhibiting a high μ FE value of 72 cm ² V −1 s −1 and I on/ I off of 2.6 × 10 ⁸ with small dual-sweep hysteresis and a subthreshold swing (SS) of 0.5 V dec −1 (discussed later). Supplementary Fig. 2 shows the plot of μ FE versus gate voltage. The corresponding output characteristics of the CsFAPEA TFT show good linearity at low drain-source voltages ( V DS) and current saturation at high V DS (Fig. 1d), suggesting low charge-carrier injection barriers and ohmic contact between the perovskite channel and gold electrodes. A reasonably low contact resistance of around 1 kΩ cm was calculated by the transmission-line method22 (Supplementary Fig. 3). The TFTs are also highly reproducible and an average μ FE value of 67.6 ± 3.6 cm ² V −1 s −1 was obtained from 50 devices in ten different batches (Fig. 1e) with an average I on/ I off value of (1.8 ± 0.3) × 10 ⁸, SS of 0.8 ± 0.2 V dec −1 and threshold voltage ( V TH) of 20.4 ± 2.9 V (statistics defined as mean ± standard deviation). Such electrical parameters are superior to those of the devices based on other perovskite semiconductors6,7,9,11,14,15,19,23,24,25,26,27, and comparable with the commercial LTPS level (Fig. 1f).

We then sought to understand the reasons behind the outstanding TFT performance. The morphologies of the different pure-Sn perovskite films are shown in Fig. 2a. The pristine 3D FA film shows poor film coverage with considerable voids and distinct grain boundaries, which is typical due to the extremely fast crystallization process, that is, rapid crystal growth occurs before nucleation is complete28. The grain boundaries are defect-rich regions, resulting in the highly p-doped character of the pristine FA films with poor charge transport property. PEA substitution greatly improved the film morphology, with much better coverage with only a few voids. It is also noticed that the grains tended to merge, forming a molten film with no discernible boundaries, similar to previous observations on optimized Sn perovskite films12,15. Generally, the crystallization control is essential to high-quality pure-Sn perovskite films12. The improved FAPEA film morphology can be attributed to the slower crystallization because the large PEA cations in the precursor retard the fast reactions between the perovskite building components29. However, the FAPEA film still appears bumpy with relatively high roughness and voids, indicating the regulation of fast crystallization is not yet sufficient20. With further Cs substitution, the optimized CsFAPEA film shows smooth morphology with full coverage. The roughness ( R q) for the CsFAPEA film is only 1.37 nm (Fig. 2b), around half that of the FAPEA film. The obtained smooth and pinhole-free morphology of the triple-cation CsFAPEA semiconducting film can benefit the charge-carrier transport in devices as well as the TFT uniformity and yield.

a- e, SEM ( a), AFM ( b), XRD ( c), ultraviolet-visible ( d) and photoluminescence ( e) data of the perovskite films. Diffraction intensities in c are multiplied by five for the FA film and divided by three for the PEA film, for clearer display, and the diffraction patterns of the (PEA) ₂SnI ₄ film (denoted as PEA) are provided for reference. All the films were controlled with a similar thickness (~30 nm) produced under the same deposition conditions for the TFT semiconducting layers.

Figure 2c shows the X-ray diffraction (XRD) patterns of different perovskite thin films. The diffraction patterns of the pristine FA thin films are mostly indexed to 3D orthorhombic ( Amm2) FASnI ₃ perovskite structure21. The FA film shows poor crystallinity and/or random texture, reflected by the weak diffraction peaks. Both FAPEA and CsFAPEA thin films show enhanced peak intensities of the 3D main body structure. Besides, we observed diffraction peaks from the two-dimensional small- n structures ( n represents the number of octahedral inorganic sheets). The FAPEA film shows heterogeneous small- n phases for both n = 1 and 2, whereas the optimized CsFAPEA film displays a pure small- n phase of n = 2 (phase distribution will be discussed later). In the ultraviolet-visible absorption and photoluminescence spectra (Fig. 2d,e), the shoulder peaks of the n = 2 phase are detected30, whereas the n = 1 signal is not detectable possibly due to the very thin film thickness and the energy transfer between phases31.

To analyse the phase distribution, grazing-incidence wide-angle X-ray scattering (GIWAXS) measurements were conducted. Incident angles of 0.2° and 2.0° were used to characterize the thin-film surface and bulk (bottom) structures, respectively. Note that the 0.2° incident angle can typically reach ~10 nm below the surface, whereas the 2.0° can detect the bottom of our thin perovskite films. Such a method has been well established and utilized previously19,20. The pristine FA film shows random and disordered orientations, as evidenced by the blurry diffraction rings, rather than discrete Bragg diffraction spots (Supplementary Fig. 5). After introducing PEA cations, the patterns obtained from the surface of the FAPEA film are mostly indexed to the 3D FASnI ₃ structure (Fig. 3a). The bottom patterns are indexed to quasi-two-dimensional small- n phases due to their higher formation energy (Fig. 3b)32. We noticed that the bottom structure of FAPEA is composed of heterogeneous phases, n = 1 and n = 2, consistent with the XRD data. The more ring-like instead of spot-like diffraction patterns also reveal that the FAPEA thin film is highly defective with a random orientation/texture. Contrastingly, the optimized CsFAPEA thin film shows more discrete Bragg spots in the diffraction patterns (Fig. 3c), indicating that Cs substitution effectively improves the cascaded perovskite structure by reducing structural imperfections and regulating the ordered crystallinity/texture. Interestingly, we observed a pure small- n phase ( n = 2) at the bottom of the CsFAPEA thin film (Fig. 3d). We also noticed that the small- n phases align parallel to the substrates. Previous studies reported two factors that increased the likelihood of mixed-dimensional perovskites to align parallel to the substrate: small film thickness (for example, <50 nm) and small n values (for example, ≤3)29, which rationalize the parallel orientation. This orientation is beneficial to a TFT device, where horizontal charge-carrier transport between the source and drain electrodes at the semiconductor/dielectric interface under gate voltage control is dominant (Fig. 1a).

a- d, GIWAXS for surface structure (incident angle of 0.2°) ( a and c) and bottom structure (incident angle of 2.0°) ( b and d) of FAPEA and CsFAPEA films. e, Dynamic light scattering data showing the particle size distribution in the precursor solutions of FAPEA and CsFAPEA. f, Illustration of the free reaction enthalpy versus the reaction coordinates, adapted from another work36.

We then sought to clarify the role of Cs substitution in the formation of high-quality cascaded perovskite films. We speculate that the differences between the crystallization kinetics of FAPEA and CsFAPEA lie in the pre- and middle-crystallization processes. Crystallization typically includes nucleation and crystal growth. It has been well recognized that fast nucleation and slow crystal growth are essential to form pinhole-free high-quality perovskite films13,33. Dynamic light scattering was used to characterize the particle size distribution in the FAPEA and CsFAPEA precursor solutions. The colloidal distribution of the FAPEA solution is mainly concentrated at ~1 nm (Fig. 3e), corresponding to a common colloidal dispersion28. The minor bump at several 10 ³ nm is related to traces of dry material powder or impurities34. Besides the typical colloidal dispersion centred at ~1 nm, the CsFAPEA precursor solution shows another particle size distribution concentrated at ~500 nm, indicating that large stable clusters with a radius of 500 nm are already formed in the precursor solution before nucleation occurs, denoted as pre-nucleation clusters35. This pre-nucleation cluster model is different from the classical crystallization scenario but similar to the precursor-to-crystalline kinetics established for calcium carbonate36. In the classical scenario, nucleation occurs when the critical nucleation enthalpy ∆ G is overcome (Fig. 3f). In the pre-nucleation cluster model, clusters are formed with a much lower activation energy barrier ∆ g, which can be overcome even by room-temperature thermal energy. Therefore, we were able to detect the clusters in the CsFAPEA precursor at room temperature and they greatly reduced the free energy barrier from precursor to crystalline. As a result, nucleation happens much easier with the subsequent more uniform crystal growth and structural stabilization in CsFAPEA (Supplementary Fig. 6). In addition, the formation of the n = 2 phase at the bottom with Cs substitution is consistent with recent experimental and theoretical studies where similar n = 2 perovskite structures were observed involving different organic A-cation combinations17,21, which have been attributed to the entropic/structural stabilization, originating from self-adjustable strain balancing37. As such, triple A-cation engineering regulates the crystallization kinetics of a pure-Sn perovskite, producing high-quality thin films with fewer structural disorders, particularly creating a low-defect phase-pure perovskite/dielectric interface, which is crucial to the achievement of high-performance perovskite TFTs.

To better understand the defect-property relationships in Sn perovskites, we conducted X-ray photoelectron spectroscopy (XPS) and Hall-effect measurements. The XPS data were used to analyse the Sn status. Sn defects are the major defects in Sn perovskites, especially Sn vacancies ( V Sn), which can be generated (1) during the perovskite structure formation due to their low formation energy and (2) from the oxidation of Sn ²⁺ to Sn ⁴⁺. As shown in Fig. 4a, the CsFAPEA film has a much lower ratio for the undercoordinated Sn with an oxidation state of δ < 2⁺ (Snδ<2+) (ref. 38), reflecting more well-coordinated Sn sublattices and a lower density of structural imperfections15. The CsFAPEA film also shows a much higher Sn ²⁺ ratio and lower Sn ⁴⁺ ratio than the other two (Supplementary Fig. 7 shows the XPS spectra). Since the V Sn defects play a dominant role in deciding the hole carrier concentration of Sn perovskites4, Hall-effect measurements were then used to investigate the hole concentrations and Hall mobilities ( μ Hall) of the different perovskite thin films (Supplementary Fig. 8). The FA film shows an average hole carrier concentration of 6.5 × 10 ¹⁶ cm −3, which decreases to 2.2 × 10 ¹⁶ cm −3 (FAPEA) and 2.4 × 10 ¹⁵ cm −3 for CsFAPEA films (Fig. 4b). This trend is a result of the decreasing density of hole generators, V Sn, agreeing well with the XPS analyses. Correspondingly, the μ Hall value of the perovskite films increases from the average μ Hall = 45 cm ² V −1 s −1 (FA; resistivity ρ = 2.1 Ω cm) to 111 cm ² V −1 s −1 (FAPEA; ρ = 2.5 Ω cm) and up to 362 cm ² V −1 s −1 for CsFAPEA films ( ρ = 6.9 Ω cm). The μ Hall value is mainly determined by the scattering time interval during charge-carrier transport, which is dominated by scattering centres, such as crystal structure disorders and ionized/charged defects3,15. Thus, the triple A-cation engineering effectively improves the perovskite film quality and reduces the density of charged defects, suppressing charge-carrier scattering and providing a rationale for the much enhanced μ Hall value.

a, b, XPS analyses on Sn status ( a) and hole concentrations and Hall mobilities ( μ Hall) of the FA, FAPEA and CsFAPEA films ( b). The error bars in b were calculated from five devices per type and the data are presented as mean ± standard deviation. c, V TH shift in FAPEA and CsFAPEA TFTs under bias stress measurement ( V GS =  V DS = −40 V). The error bars in c were calculated from five devices per time and the data are presented as mean ± standard deviation. d, Inverter diagram and optical image. e, Butterfly voltage transfer characteristics with another plotted in a mirror; V DD = 12.5 V. The inset shows the noise margin (NM), determined by the maximum size of the square that fits the voltage transfer characteristics. f, Gain = (d V out)/(d V in). g- i, NAND and NOR optical images ( g) and their output characteristics ( h and i).

A TFT can also be used as a sensitive electronic characterization platform, providing more information about defects and properties. Besides high μ FE and I on/ I off, the transfer characteristics of the CsFAPEA perovskite TFT also show minor dual-sweep hysteresis and SS of 0.5 V dec −1 (Fig. 1c). The small hysteresis mainly benefits from the reduced iodide interstitials/vacancies of iodine Frenkel defects (Supplementary Fig. 9)39, which are the main cause of hysteresis in p-channel Sn perovskite TFTs15. These iodide-related defects are preferentially formed under V Sn-rich conditions39. Based on the Hall results, the cation-engineered CsFAPEA thin films show notably reduced hole concentration ( V Sn defects), greatly benefiting the small hysteresis. Moreover, using the SS value of 0.5 V dec −1 from the optimized CsFAPEA TFT, the trap state density ( N Trap) at the dielectric/perovskite interface was calculated as 1.3 × 10 ¹² cm −2 eV −1, which is approximately half that of FAPEA (2.5 × 10 ¹² cm −2 eV −1, SS = 0.9 V dec −1; Methods provides the calculation details). This indicates that triple A-cation engineering not only enhances the film quality of Sn perovskites but also constructs a low-trap dielectric/perovskite interface for high-performance transistor applications.

The operation stability of perovskite TFTs was also assessed using bias stress testing to evaluate the practical applications. Constant negative bias voltages ( V GS =  V DS = −40 V) cause a continuous negative threshold voltage ( V TH) shift over 10 V (25% of the operation voltage) for FAPEA TFTs after 4,000 s, whereas the optimized CsFAPEA TFTs only show an average V TH shift of 3.5 V (less than 10% of the operation voltage) during the first 2,000 s and remain saturated until biased for 4,000 s (Fig. 4c and Supplementary Fig. 10a,b). The smaller V TH shift in the CsFAPEA TFTs is attributed to the lower carrier trapping in the perovskite film and at the perovskite/dielectric interface14,40. This mainly benefits from the reduced trap densities through triple A-cation engineering, as demonstrated above. Interestingly, the SS of the FAPEA TFT keeps decreasing as the biasing time increases, suggesting the passivation of interface traps. A possible reason is that the charged iodide interstitials/vacancies of iodine Frenkel defects migrate, driven by the constantly applied bias voltage, resulting in the passivation of interface traps. Contrastingly, the SS of the optimized CsFAPEA TFT remains stable during the bias stress, indicating (1) that ion migration in the optimal low-defect CsFAPEA TFT is negligible and (2) that no extra trap sites are generated in the TFT under a constant bias stress41. Therefore, the triple A-cation engineering effectively reduces the trap densities, which are created by crystal defects, structure disorders and impurities, rationalizing the excellent performance and stable operation of the CsFAPEA TFTs.

Moreover, we evaluated the long-term air, thermal and light stabilities of pure-Sn perovskite TFTs. We noticed that the TFTs show fast degradation after air exposure because of Sn ²⁺ oxidization (Supplementary Fig. 10c)4. Encouragingly, the device exhibited constant transfer characteristics after a test period of 30 days in a vacuum (~10 −6 torr; Supplementary Fig. 10d), which indicates the good intrinsic phase stability of the perovskite. We anticipate that effective encapsulations, such as those used in commercial organic light-emitting diodes, and anti-oxidation additives and stabilization strategies for Sn-based perovskites would be helpful to improve the air stability42. Additionally, the TFTs showed good thermal stability at 60 °C, that is, the typical testing temperature of TFTs1 (Supplementary Fig. 10e). This would benefit from the fact that Cs, FA and PEA cations in the triple A-cation system possess higher thermal stability (>150 °C) compared with the volatile MA cation (~80 °C)43. Although we found that the device was light sensitive (Supplementary Fig. 10f), the light instability of high-performance TFTs can be readily overcome by adopting light-shielding layers used in commercial Si and metal oxide devices1. This light-sensitive property can also enable the study of multifunctional transistors and other emerging devices, for example, phototransistors, optical-electrical dual-modulation neuromorphic devices and non-volatile photomemories44,45,46,47,48.

Going a step further, we demonstrated the processability and compatibility of the p-channel perovskite TFTs with the well-developed n-channel metal oxide ones for monolithic complementary circuit integration. We fabricated the complementary metal-oxide-semiconductor inverters by integrating the perovskite TFTs on one chip with In ₂O ₃ TFTs. The inverter diagram and optical image are shown in Fig. 4d. Figure 4e shows the standard rail-to-rail voltage transfer characteristics, where V out was either the supplied V DD or 0 (GND) with an abrupt switch at around V DD/2, indicating an ideal logic transfer from '1' to '0'. More importantly, the inverter shows a noise margin of 5.16 V, reaching as high as 82% of the ideal value ( V DD/2), which means that even if the noise causes a V in shift up to 82% of V DD/2, the inverter would still give a correct V out signal, showing the high noise-immune character. The integrated inverter also shows a high gain of 370 at V DD = 12.5 V (Fig. 4f), markedly superior to the wire-linked complementary inverter or complementary-metal-oxide-semiconductor-like inverters involving perovskite TFTs9,49. Furthermore, we integrated the complementary logic gates, namely, NAND and NOR (Fig. 4g), demonstrating the good technological adaptation of perovskite TFTs. Figure 4g shows the optical images and Fig. 4h,i plots the output characteristics of NAND and NOR, respectively, showing full rail-to-rail Boolean functionalities. The input signals are the voltage inputs for V in1 and V in2, where logic '1' and '0' represent voltages of V DD  = 10 V and 0 V, respectively.

We have reported high-performance pure-Sn perovskite TFTs by incorporating a triple A-cation combination (CsFAPEA) to construct low-defect cascaded channel films. This simple A-cation engineering creates a low-trap perovskite/dielectric interface, which is crucial for efficient charge-carrier transport and high-performance TFTs. The resulting transistors exhibit a high hole μ FE value of over 70 cm ² V −1 s −1, which is comparable with commercial LTPS-based devices. The perovskite TFTs also show good compatibility with commercial n-channel metal oxide technologies, highlighting their potential in the development of functional complementary circuits50.

Chemicals

We used the following as received without further purification: N, N-dimethylformamide (anhydrous, 99.80%, Sigma-Aldrich), dimethyl sulfoxide (anhydrous, ≥99.90%, Sigma-Aldrich), formamidinium iodide (FAI, ≥99.50%, Xi'an Polymer Light Technology), phenethylammonium iodide (≥99.50%, Xi'an Polymer Light Technology), caesium iodide (CsI, >99.90%, Xi'an Polymer Light Technology), SnI ₂ (anhydrous, beads, 99.99% trace-metal basis, Sigma-Aldrich), tin(ii) fluoride (99.00%, Sigma-Aldrich) and chlorobenzene (anhydrous, 99.80%, Sigma-Aldrich).

Precursor and device preparation

The precursor solutions were prepared by mixing FAI, phenethylammonium iodide, CsI and SnI ₂ in N, N-dimethylformamide/dimethyl sulfoxide mixed solvents at a volume ratio of 3:1. First, FAI (0.2 M), phenethylammonium iodide (0.4 M) and SnI ₂ (0.2 M, with 10 mol% tin(ii) fluoride) were dissolved in the solvents. Then, they were mixed at a volume ratio of 7:1:8 to get the FA ₇PEA ₂ (denoted to FAPEA) precursors (0.1 M). To make the (CsxFA 1-x) ₇PEA ₂ precursor, CsI (0.2 M) was prepared before being mixed at a volume ratio of FAI:CsI = (1− x): x, x = ~0-15% into the FAPEA precursors. The optimized samples made from x = 10% were denoted as CsFAPEA. Each precursor was stir heated at 60 °C for 2 h before use. Dielectric layers were the purchased 100 nm SiO ₂ on Si substrates with a capacitance of ~30 nF cm −2. For the perovskite film deposition, the SiO ₂/Si substrates (1.5 × 1.5 cm ²) were first treated with ultraviolet ozone for 30 min, then the precursor solutions were dropped on the substrates and spin coated at a speed of 4,000 r.p.m. for 60 s (acc 5 s) with 70 µl of chlorobenzene dripping after ~15 s from the beginning. Afterwards, the films were annealed at 100 °C for 10 min, constructing thin films with a similar thickness of ~30 nm. All the precursor solutions and films were prepared in a N ₂-filled glove box (O ₂ and H ₂O levels of 1-2 ppm). Then, thermal evaporation and a shadow mask were used for the Au source/drain electrode deposition. The channel width and length of the TFTs are 1,000 and 200 μm, respectively. Supplementary Fig. 4 provides the electrode geometry. Each TFT was tip scratched before measurement to reduce the gate leakage and the influence of fringe effect. Smaller channel lengths would cause the maximum drain current beyond the equipment test limit (10 −2 A). For the complementary inverter and logic gates integration, we first evaporated patterned nickel (20 nm) as the bottom gate through a designed shadow mask, then used hafnium oxide (100 nm) by atomic layer deposition as the dielectric layer, solution-processed In ₂O ₃ TFTs patterned by photolithography as n-channel and self-patterned perovskite TFTs as the p-channel and eventually evaporated gold through another designed shadow mask as source and drain electrodes.

Characterizations

The XRD patterns of the film were recorded using a Rigaku D/MAX 2600V with Cu Kα ( λ = 1.5406 Å) radiation. The SEM images were obtained using a field-emission scanning electron microscope (Hitachi S4800). AFM data were collected using atomic force microscopy (Nanoscope V Multimode 8, Bruker). XPS characterizations were conducted using a VersaProbe Scanning Microprobe under a vacuum (10 −8 torr). The Hall measurements were performed using the van der Pauw method, using a 0.51 T magnet and a bespoke sample holder in a N ₂-filled glove box at room temperature. The electrical signal during the Hall measurement was obtained using a Keithley 4200-SCS and probe station (MST 4000A, MS TECH). Dynamic light scattering measurements were conducted using a Zetasizer Nano (Malvern Instruments). For the GIWAXS analysis, the X-ray beam energy was 9.84 eV, corresponding to a wavelength of 1.26 Å, and the sample-detector distance was 208.76 mm. Transistor transfer characteristics were measured using a semiconductor parameter analyser (Keithley 4200-SCS) in a N ₂-filled glove box at room temperature in the continuous mode. The saturation TFT mobility was calculated as

where L, W, C i, I DS and V GS are the channel length, channel width, dielectric areal capacitance, source-drain current and gate-source voltage, respectively. The SS value was extracted from the reciprocal of a subthreshold slope, in V dec ⁻¹. The V TH value was extracted by linear fitting | I DS| 1/2 versus V GS. The perovskite/dielectric interface trap density can be estimated from \({N}_{{{\rm{trap}}}}=\left[\frac{{{\rm{SS}}q}{{\log }}(e)}{{kT}}-1\right]\frac{{C}_{{\rm{i}}}}{q}\), where q is the electron charge, k is the Boltzmann constant and e is the base of the natural logarithm.

This study was supported by the Ministry of Science and ICT through the National Research Foundation, funded by the Korean government (2021R1A2C3005401, RS-2023-00216352 and RS-2023-00260608; to Y.-Y.N.). This work was supported by the BK21 FOUR Program for Education Program for Innovative Chemical Engineering Leaders of the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT to A.L. and H. Z.). This research was also supported by the Samsung Display Corporation (to Y.-Y.N.). H.Z. thanks J. Kim and J.-Y. Go for help with the GIWAXS measurements and analyses, and also to G.-S. Ryu for help with the shadow mask design.

Authors and Affiliations

1. Department of Chemical Engineering, Pohang University of Science and Technology, Pohang, Republic of Korea

Huihui Zhu, Wonryeol Yang, Youjin Reo, Ao Liu & Yong-Young Noh

2. Shanghai Synchrotron Radiation Facility (SSRF), Zhangjiang Lab, Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai, China

Guanhaojie Zheng

3. University of Chinese Academy of Sciences, Beijing, China

Guanhaojie Zheng

4. Institute of Fundamental and Frontier Sciences, University of Electronic Science and Technology of China, Chengdu, China

Sai Bai

Contributions

H.Z. and Y.-Y.N. conceived the study. H.Z. performed the experiments. A.L. and W.Y. helped with the experiment. A.L., Y.R. and G.Z. assisted with the characterizations and analyses. A.L. and S.B. helped with the analyses and discussion. H.Z., A.L. and Y.-Y.N. wrote the manuscript. All the authors contributed to the discussion and approved the final version of the manuscript.

Corresponding authors

Correspondence to Ao Liu or Yong-Young Noh.

Competing interests

The authors declare no competing interests.

Peer review information

Nature Electronics thanks Mallory Mativenga, Anita Ho-Baillie and Kamal Asadifor for their contribution to the peer review of this work.

Publisher's note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.
Reprints and permissions

# data[].attributes.attachment_link.title
Tin perovskite transistors and complementary circuits based on A-site cation engineering - Nature Electronics

# data[].attributes.attachment_link.description
Tin halide perovskites have the general chemical formula ASnX3, where A is a monovalent cation and X is a monovalent halide anion. These semiconducting materials can be used to fabricate p-type transistors at low cost and temperature and could be potentially integrated with n-type oxide-based transistors to create complementary circuits.