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Modern Microprocessors - A 90-Minute Guide!

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A brief, pulls-no-punches, fast-paced introduction to the main design aspects of modern processor microarchitecture.

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The constant push to boost computing performance and efficiency has taxed the venerable x86 architecture and presented modern processor design with new challenges.

It's far from obsolete, but designers working with x86 systems face major challenges packing more transistors into less space while trying to use less energy, given current fabrication technologies. Enterprise system designers are discovering that a single processor isn't necessarily the most efficient answer for computing tasks related to big data, generic private cloud, high performance computing or Web serving. Rather, matching a particular processor design to the specific task can provide superior computing performance -- often requiring just a fraction of the energy used for traditional x86 processors.

This is not a new concept. Purpose-built and reduced instruction set processors existed in everything from printers to network devices to industrial systems long before the rise of x86. But it was really the recent smartphone and tablet processors that demonstrated capable processing performance with miniscule energy needs. Those design philosophies are taking tomorrow's enterprise processors in new and exciting directions, and providing designers with a rich array of processor alternatives for next-generation data center systems.

Purpose-built x86 processors

Consider the emergence of purpose-built processors that are designed to meet the unique computing needs of specific device types while maintaining compatibility with x86 instruction sets. A common example of this philosophy is Intel's Atom family. Initial Atom releases were focused on mobile device and tablet applications, but second-generation Atom variants provide support for several enterprise-class tasks.

For example, the Atom Avoton is planned for microservers -- an emerging low-power, scalable computing appliance designed for easy installation and maintenance. A microserver may include the operating system, hardware and applications already installed by the system vendor for relatively lightweight tasks like serving up HTML webpages or handling individual compute tasks in a big data analysis. The Avoton is noteworthy for enterprise use because it adds 64-bit support to the low-power Atom core and Ethernet controllers for high-throughput networking and virtualization support. Avoton chips will also use a new 22 nanometer fabrication process that allows transistors to be stacked rather than placed side-by-side. This brings lower energy demands and shorter paths between transistors for better performance.

Another example is the Atom S12x9 family, which is slated to provide 40 lanes of PCI Express (PCIe) between the processor and I/O devices such as disk drives. These Atoms also tout hardware RAID acceleration and native dual-casting, which allows data to be read from one location and written to two locations simultaneously -- ideal for data protection technologies like memory mirroring. This emphasis on I/O support and data protection makes the S12x9 family of Atoms suitable for use in storage subsystems like storage servers.

Then there's the Atom Rangeley processor, which is intended for networking appliances like routers, switches and security devices. Its specialty is processing traffic-intensive workloads using a cryptographic engine that supports 128-, 192- and 256-bit AES, 3DES, DES and Kasumi ciphers along with features like authentication, public key encryption and random number generation.

Purpose-built processors are typically multicore devices built with a system-on-chip (SoC) approach that incorporates almost all of the major components needed to implement a complete computer into the processor package itself. For example, the Avoton and Rangeley are expected to incorporate dual-channel double data rate version 3 (DDR3) memory controllers supporting up to 64 GB of error-correcting code (ECC) memory along with some PCIe controllers, SATA controllers, gigabit Ethernet controllers, USB and other legacy I/O (such as SMBus and UART) controllers. SoC integration decreases the overall chip count in the system, lowers costs, and improves performance due to shorter connection paths between the processor die and other functions.

An increasing number of modern SoC designs also incorporate a graphics processing unit (GPU) to assist in visualization-related tasks --though the Atom variants above do not. A good use might include a desktop virtualization (VDI) server that must deliver more complex renderings, images or real-time media like video that would bog down a conventional processor without graphics assistance. GPUs are also appearing in mainstream x86 server processors like Intel's newest Xeon E3 and AMD's emerging Opteron X processor series.

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Modern processor design means integration, efficiency

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The constant push to boost computing performance and efficiency has taxed the venerable x86 architecture and presented modern processor design with new challenges. It's far from obsolete, but designers working with x86 systems face major challenges packing more transistors into less space while trying to use less energy, given current fabrication technologies.

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For nearly 10 years, computer processors have been getting faster by using multiple cores rather than raising their individual speeds. This measure makes our PCs and smartphones more power-efficient, but also makes it much trickier to write programs that take full advantage of their hardware. Swarm, a new chip design developed at MIT, could now come to the rescue and unleash the full power of parallel processing for up to 75-fold speedups, while requiring programmers to write a fraction of the code.

Developed by Prof. Daniel Sanchez and team, Swarm is a 64-core chip that includes specialized circuitry for both executing and prioritizing tasks in a simple and efficient manner, taking the onus off software developers.

Writing software for a multi-core chip is a lot like coordinating a complex team project: not all tasks can be delegated, and the ones that can must be carefully split among team members. With software, this sort of planning can be complicated, time-consuming, and add substantial overheads that end up slowing the software's execution. For this reason, parallel programming is usually convenient only for large tasks that number thousands of instructions.

In addition, developers must also face the fickle problem of handling data conflicts. A task might request to access and edit a piece of data that is currently being worked on by another task. To avoid corrupting the data, programmers must manually handle priorities between tasks and make sure shared resources can only be accessed by one task at a time (forcing other tasks to idly wait for their turn).

The Swarm architecture tackles these problems by featuring specialized circuitry for delegating even the smallest of tasks very efficiently and enforcing a strict priority among them. As a result, programmers can execute tasks in parallel with little overhead, making software run up to tens times faster.

"Swarm has two advantages over conventional multicores," Sanchez tells us. "First, Swarm supports tiny tasks, as small as tens of instructions, efficiently. By contrast, current multicores need larger tasks (thousands of instructions or more) to operate efficiently. Supporting smaller tasks allows more parallelism, simply because there often is a lot of parallelism inside each large task.

"Second, Swarm enforces a global order among these tasks. By contrast, current multicores cannot support ordered execution efficiently, especially with small tasks."

This global order is very useful for handling data conflicts. After tasks are automatically prioritized (according to a metric set by the developer), Swarm starts working on the highest-priority subroutines in parallel, taking advantage of its 64 cores. If data conflicts arise, they can now be handled automatically: for instance, if a low-priority task modifies data that is later accessed by a high-priority task, the data value is temporarily reverted to allow the critical tasks to complete sooner.

To test their new architecture, Sanchez and team compared Swarm versions of six common algorithms to their highly-optimized parallel counterparts. Remarkably, the Swarm software executed the same task three to 18 times faster, despite requiring only about one tenth of the code. In one case, the system was able to achieve an impressive 75-fold speedup on an algorithm that computer scientists had so far failed to parallelize.

The researchers suspect that the complexity of developing software for multi-core systems may have been one of the key reasons why chip manufacturers have been holding back on the number of cores. Swarm could now solve this problem and pave the way for general-purpose chips with a huge number of cores.

"In an upcoming paper, we demonstrate scalability to hundreds of cores," Sanchez tells us. "In principle, this style of architecture can scale to even larger systems (e.g., multiple chips and boards) as long as the application has enough parallelism."

The researchers are currently working on techniques to make Swarm even more efficient by reducing data movement and exploring new programming models.

A paper describing the advance appears in the latest edition of the journal .

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MIT's Swarm chip architecture boosts multi-core CPUs

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For nearly 10 years, computer processors have been getting faster by using multiple cores rather than raising their individual speeds. This measure makes our PCs and smartphones more power-efficient, but also makes it much trickier to write programs that take full advantage of their hardware.

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While Intel has made some noise at CES 2017 with a host of PCs using its seventh-generation Core processors, AMD hasn't been sitting still. With its introduction of its Ryzen CPU, AMD has countered Intel's best with some excellent performance of its own.

Ryzen represents a more aggressive improvement over AMD's previous architecture, Excavator, with the new Zen chips offering a full 40 percent improvement. That's much more significant than Intel's more conservative improvements with its latest generation of CPUs, which focused on smaller performance increases and better mobile battery life. This is an important accomplishment for AMD, because apparently, it's going to have to last for at least four years, as PCWorld reports.

The news came during CES 2017, where AMD's computing and graphics senior vice president and general manager Jim Anderson discussed the new architecture. As he put it, comparing AMD's process to Intel's "tick-tock" development cycle that was actually skipped this time around, "We're not going tick-tock. Zen is going to be tock, tock, tock."

While Intel's methodology usually results in a brand new architecture every two years, AMD has averaged closer to three to four years. It's Opteron and Athlon architectures lasted from 2003 until 2007, and its K10 lasted from 2007 until 2010. The bottom line is that AMD simply must introduce impressive new performance metrics each cycle because its new architectures must remain competitive for far longer.

With Zen and Ryzen, AMD has taken the tactic of improving not only clock speeds but also making the chips better at guessing at what data will be processed next, called "branch prediction," as well as build in the ability for chips to process more information at a time. That means AMD is focusing on going beyond Moore's Law, which has predicted increased processor performance in PCs for decades, into "Moore's Law Plus" that focuses on more than just manufacturing processes.

Judging by CES 2017, AMD's efforts are paying dividends. A number of leading motherboard makers announced Ryzen-based components, with a total of 16 AM4-based solutions that are primed to plug in new Ryzen desktop processors. Not only AMD's newest CPUs are supported in this year's round of components, but also other high-end PC parts such as PCIe 3.0, M.2 SATA devices, USB Type-C ports with Thunderbolt 3, and more.

Clearly, AMD is not messing around in making Ryzen a real product. As Anderson put it, "We're not going to do a paper launch [where products are announced long before they actually ship]. We've done that before. We're not going to mess with it." That means that AMD and its customers will be able to squeeze every bit of life out of the Zen architecture for its entire four-year lifespan.

Competition is a good thing, and so AMD's efforts are welcome in pushing PC's forward. Intel isn't standing still itself, of course, with its own upcoming advancements such as the 10mm manufacturing process coming with its own next generation of CPUs. But AMD is apparently confident that it's positioned itself well to remain relevant in PCs well into the next decade.

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AMD's new Zen CPU architecture will last until 2020 and beyond

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While Intel has made some noise at CES 2017 with a host of PCs using its seventh-generation Core processors, AMD hasn't been sitting still. With its introduction of its Ryzen CPU, AMD has countered Intel's best with some excellent performance of its own.

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Contemporary Processors